Revert "[SROA] Optimize reloaded values in allocas that escape into readonly nocapture calls. (#116645)"
Causing buffer overflow: SUMMARY: AddressSanitizer: heap-buffer-overflow llvm/lib/Transforms/Scalar/SROA.cpp:5552:35 This reverts commit 5e247d726d7a54cf0acc997bc17b50e7494e6fa3.
This commit is contained in:
Kirill Stoimenov
parent
7071cd3885
commit
e3676aa21f
@ -64,9 +64,6 @@ public:
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/// Is the pointer escaped at some point?
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bool isEscaped() const { return EscapedInfo != nullptr; }
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/// Is the pointer escaped into a read-only nocapture call at some point?
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bool isEscapedReadOnly() const { return EscapedReadOnly != nullptr; }
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/// Get the instruction causing the visit to abort.
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/// \returns a pointer to the instruction causing the abort if one is
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/// available; otherwise returns null.
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@ -77,10 +74,6 @@ public:
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/// is available; otherwise returns null.
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Instruction *getEscapingInst() const { return EscapedInfo; }
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/// Get the instruction causing the pointer to escape which is a read-only
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/// nocapture call.
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Instruction *getEscapedReadOnlyInst() const { return EscapedReadOnly; }
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/// Mark the visit as aborted. Intended for use in a void return.
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/// \param I The instruction which caused the visit to abort, if available.
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void setAborted(Instruction *I) {
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@ -95,12 +88,6 @@ public:
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EscapedInfo = I;
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}
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/// Mark the pointer as escaped into a readonly-nocapture call.
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void setEscapedReadOnly(Instruction *I) {
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assert(I && "Expected a valid pointer in setEscapedReadOnly");
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EscapedReadOnly = I;
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}
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/// Mark the pointer as escaped, and the visit as aborted. Intended
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/// for use in a void return.
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/// \param I The instruction which both escapes the pointer and aborts the
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@ -113,7 +100,6 @@ public:
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private:
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Instruction *AbortedInfo = nullptr;
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Instruction *EscapedInfo = nullptr;
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Instruction *EscapedReadOnly = nullptr;
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};
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protected:
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@ -188,13 +188,6 @@ public:
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/// Return false if a sub-class wants to keep one of the loads/stores
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/// after the SSA construction.
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virtual bool shouldDelete(Instruction *I) const { return true; }
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/// Return the value to use for the point in the code that the alloca is
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/// positioned. This will only be used if an Alloca is included in Insts,
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/// otherwise the value of a uninitialized load will be assumed to be poison.
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virtual Value *getValueToUseForAlloca(Instruction *AI) const {
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return nullptr;
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}
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};
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} // end namespace llvm
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@ -43,7 +43,6 @@
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#include "llvm/Analysis/GlobalsModRef.h"
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#include "llvm/Analysis/Loads.h"
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#include "llvm/Analysis/PtrUseVisitor.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constant.h"
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@ -84,7 +83,6 @@
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#include "llvm/Transforms/Utils/BasicBlockUtils.h"
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#include "llvm/Transforms/Utils/Local.h"
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#include "llvm/Transforms/Utils/PromoteMemToReg.h"
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#include "llvm/Transforms/Utils/SSAUpdater.h"
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#include <algorithm>
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#include <cassert>
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#include <cstddef>
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@ -248,7 +246,6 @@ private:
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bool presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS);
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AllocaInst *rewritePartition(AllocaInst &AI, AllocaSlices &AS, Partition &P);
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bool splitAlloca(AllocaInst &AI, AllocaSlices &AS);
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bool propagateStoredValuesToLoads(AllocaInst &AI, AllocaSlices &AS);
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std::pair<bool /*Changed*/, bool /*CFGChanged*/> runOnAlloca(AllocaInst &AI);
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void clobberUse(Use &U);
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bool deleteDeadInstructions(SmallPtrSetImpl<AllocaInst *> &DeletedAllocas);
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@ -601,7 +598,6 @@ public:
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/// If this is true, the slices are never fully built and should be
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/// ignored.
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bool isEscaped() const { return PointerEscapingInstr; }
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bool isEscapedReadOnly() const { return PointerEscapingInstrReadOnly; }
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/// Support for iterating over the slices.
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/// @{
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@ -684,7 +680,6 @@ private:
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/// store a pointer to that here and abort trying to form slices of the
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/// alloca. This will be null if the alloca slices are analyzed successfully.
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Instruction *PointerEscapingInstr;
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Instruction *PointerEscapingInstrReadOnly;
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/// The slices of the alloca.
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///
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@ -1395,18 +1390,6 @@ private:
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/// Disable SROA entirely if there are unhandled users of the alloca.
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void visitInstruction(Instruction &I) { PI.setAborted(&I); }
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void visitCallBase(CallBase &CB) {
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// If the call operand is NoCapture ReadOnly, then we mark it as
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// EscapedReadOnly.
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if (CB.doesNotCapture(U->getOperandNo()) &&
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CB.onlyReadsMemory(U->getOperandNo())) {
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PI.setEscapedReadOnly(&CB);
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return;
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}
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Base::visitCallBase(CB);
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}
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};
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AllocaSlices::AllocaSlices(const DataLayout &DL, AllocaInst &AI)
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@ -1414,7 +1397,7 @@ AllocaSlices::AllocaSlices(const DataLayout &DL, AllocaInst &AI)
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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AI(AI),
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#endif
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PointerEscapingInstr(nullptr), PointerEscapingInstrReadOnly(nullptr) {
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PointerEscapingInstr(nullptr) {
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SliceBuilder PB(DL, AI, *this);
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SliceBuilder::PtrInfo PtrI = PB.visitPtr(AI);
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if (PtrI.isEscaped() || PtrI.isAborted()) {
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@ -1425,7 +1408,6 @@ AllocaSlices::AllocaSlices(const DataLayout &DL, AllocaInst &AI)
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assert(PointerEscapingInstr && "Did not track a bad instruction");
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return;
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}
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PointerEscapingInstrReadOnly = PtrI.getEscapedReadOnlyInst();
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llvm::erase_if(Slices, [](const Slice &S) { return S.isDead(); });
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@ -1463,9 +1445,6 @@ void AllocaSlices::print(raw_ostream &OS) const {
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return;
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}
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if (PointerEscapingInstrReadOnly)
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OS << "Escapes into ReadOnly: " << *PointerEscapingInstrReadOnly << "\n";
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OS << "Slices of alloca: " << AI << "\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I)
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print(OS, I);
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@ -5475,86 +5454,6 @@ void SROA::clobberUse(Use &U) {
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}
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}
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/// A basic LoadAndStorePromoter that does not remove store nodes.
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class BasicLoadAndStorePromoter : public LoadAndStorePromoter {
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public:
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BasicLoadAndStorePromoter(ArrayRef<const Instruction *> Insts, SSAUpdater &S,
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Type *ZeroType)
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: LoadAndStorePromoter(Insts, S), ZeroType(ZeroType) {}
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bool shouldDelete(Instruction *I) const override {
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return !isa<StoreInst>(I) && !isa<AllocaInst>(I);
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}
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Value *getValueToUseForAlloca(Instruction *I) const override {
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return UndefValue::get(ZeroType);
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}
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private:
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Type *ZeroType;
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};
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bool SROA::propagateStoredValuesToLoads(AllocaInst &AI, AllocaSlices &AS) {
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// Look through each "partition", looking for slices with the same start/end
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// that do not overlap with any before them. The slices are sorted by
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// increasing beginOffset. We don't use AS.partitions(), as it will use a more
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// sophisticated algorithm that takes splittable slices into account.
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auto PartitionBegin = AS.begin();
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auto PartitionEnd = PartitionBegin;
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uint64_t BeginOffset = PartitionBegin->beginOffset();
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uint64_t EndOffset = PartitionBegin->endOffset();
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while (PartitionBegin != AS.end()) {
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bool AllSameAndValid = true;
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SmallVector<Instruction *> Insts;
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Type *PartitionType = nullptr;
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while (PartitionEnd != AS.end() &&
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(PartitionEnd->beginOffset() < EndOffset ||
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PartitionEnd->endOffset() <= EndOffset)) {
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if (AllSameAndValid) {
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AllSameAndValid &= PartitionEnd->beginOffset() == BeginOffset &&
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PartitionEnd->endOffset() == EndOffset;
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Instruction *User =
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cast<Instruction>(PartitionEnd->getUse()->getUser());
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if (auto *LI = dyn_cast<LoadInst>(User)) {
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Type *UserTy = LI->getType();
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// LoadAndStorePromoter requires all the types to be the same.
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if (!LI->isSimple() || (PartitionType && UserTy != PartitionType))
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AllSameAndValid = false;
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PartitionType = UserTy;
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Insts.push_back(User);
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} else if (auto *SI = dyn_cast<StoreInst>(User)) {
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Type *UserTy = SI->getValueOperand()->getType();
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if (!SI->isSimple() || PartitionType && UserTy != PartitionType)
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AllSameAndValid = false;
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PartitionType = UserTy;
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Insts.push_back(User);
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} else if (!isAssumeLikeIntrinsic(User)) {
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AllSameAndValid = false;
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}
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}
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EndOffset = std::max(EndOffset, PartitionEnd->endOffset());
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++PartitionEnd;
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}
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// So long as all the slices start and end offsets matched, update loads to
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// the values stored in the partition.
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if (AllSameAndValid && !Insts.empty()) {
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LLVM_DEBUG(dbgs() << "Propagate values on slice [" << BeginOffset << ", "
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<< EndOffset << ")\n");
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SmallVector<PHINode *, 4> NewPHIs;
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SSAUpdater SSA(&NewPHIs);
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Insts.push_back(&AI);
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BasicLoadAndStorePromoter Promoter(Insts, SSA, PartitionType);
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Promoter.run(Insts);
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}
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// Step on to the next partition.
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PartitionBegin = PartitionEnd;
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BeginOffset = PartitionBegin->beginOffset();
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EndOffset = PartitionBegin->endOffset();
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}
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return true;
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}
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/// Analyze an alloca for SROA.
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///
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/// This analyzes the alloca to ensure we can reason about it, builds
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@ -5595,11 +5494,6 @@ SROA::runOnAlloca(AllocaInst &AI) {
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if (AS.isEscaped())
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return {Changed, CFGChanged};
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if (AS.isEscapedReadOnly()) {
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Changed |= propagateStoredValuesToLoads(AI, AS);
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return {Changed, CFGChanged};
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}
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// Delete all the dead users of this alloca before splitting and rewriting it.
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for (Instruction *DeadUser : AS.getDeadUsers()) {
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// Free up everything used by this instruction.
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@ -412,13 +412,9 @@ void LoadAndStorePromoter::run(const SmallVectorImpl<Instruction *> &Insts) {
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if (StoreInst *SI = dyn_cast<StoreInst>(User)) {
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updateDebugInfo(SI);
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SSA.AddAvailableValue(BB, SI->getOperand(0));
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} else if (auto *AI = dyn_cast<AllocaInst>(User)) {
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// We treat AllocaInst as a store of an getValueToUseForAlloca value.
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SSA.AddAvailableValue(BB, getValueToUseForAlloca(AI));
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} else {
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} else
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// Otherwise it is a load, queue it to rewrite as a live-in load.
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LiveInLoads.push_back(cast<LoadInst>(User));
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}
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BlockUses.clear();
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continue;
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}
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@ -426,7 +422,7 @@ void LoadAndStorePromoter::run(const SmallVectorImpl<Instruction *> &Insts) {
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// Otherwise, check to see if this block is all loads.
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bool HasStore = false;
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for (Instruction *I : BlockUses) {
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if (isa<StoreInst>(I) || isa<AllocaInst>(I)) {
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if (isa<StoreInst>(I)) {
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HasStore = true;
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break;
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}
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@ -472,12 +468,6 @@ void LoadAndStorePromoter::run(const SmallVectorImpl<Instruction *> &Insts) {
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// Remember that this is the active value in the block.
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StoredValue = SI->getOperand(0);
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} else if (auto *AI = dyn_cast<AllocaInst>(&I)) {
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// Check if this an alloca, in which case we treat it as a store of
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// getValueToUseForAlloca.
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if (!isInstInList(AI, Insts))
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continue;
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StoredValue = getValueToUseForAlloca(AI);
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}
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}
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@ -9,18 +9,19 @@ define i32 @alloca_used_in_call(ptr %data, i64 %n) {
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; CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
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; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
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; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
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; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[I0:%.*]] = call i32 @user_of_alloca(ptr [[RETVAL]])
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; CHECK-NEXT: ret i32 [[RDX_INC]]
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; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
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; CHECK-NEXT: ret i32 [[I1]]
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;
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entry:
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%retval = alloca i32, align 4
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@ -137,18 +138,19 @@ define i32 @alloca_not_captured_and_readonly_as_per_operand_attr(ptr %data, i64
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; CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
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; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
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; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
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; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[I0:%.*]] = call i32 @capture_of_alloca(ptr nocapture readonly [[RETVAL]])
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; CHECK-NEXT: ret i32 [[RDX_INC]]
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; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
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; CHECK-NEXT: ret i32 [[I1]]
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;
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entry:
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%retval = alloca i32, align 4
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@ -265,18 +267,19 @@ define i32 @alloca_with_gep_used_in_call(ptr %data, i64 %n) {
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; CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
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; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
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; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
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; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[I0:%.*]] = call i32 @user_of_alloca(ptr [[RETVAL]])
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; CHECK-NEXT: ret i32 [[RDX_INC]]
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; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
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; CHECK-NEXT: ret i32 [[I1]]
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;
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entry:
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%retval = alloca i32, align 4
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@ -350,11 +353,11 @@ define i32 @alloca_used_in_maybe_throwing_call(ptr %data, i64 %n) personality pt
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; CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
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; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
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; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
|
||||
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
|
||||
@ -369,7 +372,8 @@ define i32 @alloca_used_in_maybe_throwing_call(ptr %data, i64 %n) personality pt
|
||||
; CHECK-NEXT: catch ptr null
|
||||
; CHECK-NEXT: br label [[END]]
|
||||
; CHECK: end:
|
||||
; CHECK-NEXT: ret i32 [[RDX_INC]]
|
||||
; CHECK-NEXT: [[I2:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: ret i32 [[I2]]
|
||||
;
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
@ -409,11 +413,11 @@ define i32 @alloca_used_in_maybe_throwing_call_with_same_dests(ptr %data, i64 %n
|
||||
; CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
|
||||
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
|
||||
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
|
||||
@ -426,7 +430,8 @@ define i32 @alloca_used_in_maybe_throwing_call_with_same_dests(ptr %data, i64 %n
|
||||
; CHECK-NEXT: catch ptr null
|
||||
; CHECK-NEXT: br label [[END]]
|
||||
; CHECK: end:
|
||||
; CHECK-NEXT: ret i32 [[RDX_INC]]
|
||||
; CHECK-NEXT: [[I2:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: ret i32 [[I2]]
|
||||
;
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
@ -467,11 +472,11 @@ define [2 x i32] @part_of_alloca_used_in_call(ptr %data, i64 %n) {
|
||||
; CHECK-NEXT: [[RETVAL:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i64 0, i64 1
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
|
||||
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
|
||||
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
|
||||
@ -479,9 +484,11 @@ define [2 x i32] @part_of_alloca_used_in_call(ptr %data, i64 %n) {
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: [[I0:%.*]] = call i32 @user_of_alloca(ptr [[RETVAL]])
|
||||
; CHECK-NEXT: [[I1_FCA_0_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 0
|
||||
; CHECK-NEXT: [[I1_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 0, 0
|
||||
; CHECK-NEXT: [[I1_FCA_0_LOAD:%.*]] = load i32, ptr [[I1_FCA_0_GEP]], align 4
|
||||
; CHECK-NEXT: [[I1_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 [[I1_FCA_0_LOAD]], 0
|
||||
; CHECK-NEXT: [[I1_FCA_1_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 1
|
||||
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[RDX_INC]], 1
|
||||
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
|
||||
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
|
||||
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
|
||||
;
|
||||
entry:
|
||||
@ -518,11 +525,11 @@ define [2 x i32] @all_parts_of_alloca_used_in_call_with_multiple_args(ptr %data,
|
||||
; CHECK-NEXT: [[RETVAL:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i64 0, i64 1
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
|
||||
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
|
||||
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
|
||||
@ -530,9 +537,11 @@ define [2 x i32] @all_parts_of_alloca_used_in_call_with_multiple_args(ptr %data,
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: [[I0:%.*]] = call i32 @user_of_alloca_with_multiple_args(ptr [[RETVAL]], ptr [[RETVAL_FULL]])
|
||||
; CHECK-NEXT: [[I1_FCA_0_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 0
|
||||
; CHECK-NEXT: [[I1_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 0, 0
|
||||
; CHECK-NEXT: [[I1_FCA_0_LOAD:%.*]] = load i32, ptr [[I1_FCA_0_GEP]], align 4
|
||||
; CHECK-NEXT: [[I1_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 [[I1_FCA_0_LOAD]], 0
|
||||
; CHECK-NEXT: [[I1_FCA_1_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 1
|
||||
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[RDX_INC]], 1
|
||||
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
|
||||
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
|
||||
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
|
||||
;
|
||||
entry:
|
||||
@ -679,11 +688,11 @@ define [2 x i32] @part_of_alloca_used_in_call_with_multiple_args(ptr %data, i64
|
||||
; CHECK-NEXT: [[RETVAL:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i64 0, i64 1
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
|
||||
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
|
||||
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
|
||||
@ -691,9 +700,11 @@ define [2 x i32] @part_of_alloca_used_in_call_with_multiple_args(ptr %data, i64
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: [[I0:%.*]] = call i32 @user_of_alloca_with_multiple_args(ptr [[RETVAL]], ptr [[RETVAL]])
|
||||
; CHECK-NEXT: [[I1_FCA_0_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 0
|
||||
; CHECK-NEXT: [[I1_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 0, 0
|
||||
; CHECK-NEXT: [[I1_FCA_0_LOAD:%.*]] = load i32, ptr [[I1_FCA_0_GEP]], align 4
|
||||
; CHECK-NEXT: [[I1_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 [[I1_FCA_0_LOAD]], 0
|
||||
; CHECK-NEXT: [[I1_FCA_1_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 1
|
||||
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[RDX_INC]], 1
|
||||
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
|
||||
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
|
||||
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
|
||||
;
|
||||
entry:
|
||||
@ -731,11 +742,11 @@ define [2 x i32] @all_parts_of_alloca_used_in_calls_with_multiple_args(ptr %data
|
||||
; CHECK-NEXT: [[RETVAL:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i64 0, i64 1
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RDX_INC:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i64 [[INDVARS_IV]]
|
||||
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: [[RDX:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[RDX_INC:%.*]] = add nsw i32 [[RDX]], [[LD]]
|
||||
; CHECK-NEXT: store i32 [[RDX_INC]], ptr [[RETVAL]], align 4
|
||||
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
|
||||
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
|
||||
@ -745,9 +756,11 @@ define [2 x i32] @all_parts_of_alloca_used_in_calls_with_multiple_args(ptr %data
|
||||
; CHECK-NEXT: [[I1:%.*]] = call i32 @user_of_alloca_with_multiple_args(ptr [[RETVAL_FULL]], ptr [[RETVAL]])
|
||||
; CHECK-NEXT: [[I2:%.*]] = call i32 @capture_of_alloca(ptr [[SOME_ANOTHER_ALLOCA_FULL]])
|
||||
; CHECK-NEXT: [[I3_FCA_0_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 0
|
||||
; CHECK-NEXT: [[I3_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 0, 0
|
||||
; CHECK-NEXT: [[I3_FCA_0_LOAD:%.*]] = load i32, ptr [[I3_FCA_0_GEP]], align 4
|
||||
; CHECK-NEXT: [[I3_FCA_0_INSERT:%.*]] = insertvalue [2 x i32] poison, i32 [[I3_FCA_0_LOAD]], 0
|
||||
; CHECK-NEXT: [[I3_FCA_1_GEP:%.*]] = getelementptr inbounds [2 x i32], ptr [[RETVAL_FULL]], i32 0, i32 1
|
||||
; CHECK-NEXT: [[I3_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I3_FCA_0_INSERT]], i32 [[RDX_INC]], 1
|
||||
; CHECK-NEXT: [[I3_FCA_1_LOAD:%.*]] = load i32, ptr [[I3_FCA_1_GEP]], align 4
|
||||
; CHECK-NEXT: [[I3_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I3_FCA_0_INSERT]], i32 [[I3_FCA_1_LOAD]], 1
|
||||
; CHECK-NEXT: ret [2 x i32] [[I3_FCA_1_INSERT]]
|
||||
;
|
||||
entry:
|
||||
@ -838,7 +851,8 @@ define i8 @dont_transform_load_only() {
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
; CHECK-NEXT: call void @byte_user_of_alloca(ptr [[A]])
|
||||
; CHECK-NEXT: ret i8 undef
|
||||
; CHECK-NEXT: [[R:%.*]] = load i8, ptr [[A]], align 1
|
||||
; CHECK-NEXT: ret i8 [[R]]
|
||||
;
|
||||
entry:
|
||||
%a = alloca i8
|
||||
@ -852,7 +866,8 @@ define i8 @transform_load_and_store() {
|
||||
; CHECK-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
; CHECK-NEXT: store i8 0, ptr [[A]], align 1
|
||||
; CHECK-NEXT: call void @byte_user_of_alloca(ptr [[A]])
|
||||
; CHECK-NEXT: ret i8 0
|
||||
; CHECK-NEXT: [[R:%.*]] = load i8, ptr [[A]], align 1
|
||||
; CHECK-NEXT: ret i8 [[R]]
|
||||
;
|
||||
entry:
|
||||
%a = alloca i8
|
||||
|
||||
@ -8,7 +8,8 @@ define i32 @simple() {
|
||||
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
; CHECK-NEXT: store i32 0, ptr [[A]], align 4
|
||||
; CHECK-NEXT: call void @callee(ptr [[A]])
|
||||
; CHECK-NEXT: ret i32 0
|
||||
; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[A]], align 4
|
||||
; CHECK-NEXT: ret i32 [[L1]]
|
||||
;
|
||||
%a = alloca i32
|
||||
store i32 0, ptr %a
|
||||
@ -39,7 +40,9 @@ define i32 @twoalloc() {
|
||||
; CHECK-NEXT: [[B:%.*]] = getelementptr i32, ptr [[A]], i32 1
|
||||
; CHECK-NEXT: store i32 1, ptr [[B]], align 4
|
||||
; CHECK-NEXT: call void @callee(ptr [[A]])
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 0, 1
|
||||
; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[A]], align 4
|
||||
; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[B]], align 4
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 [[L1]], [[L2]]
|
||||
; CHECK-NEXT: ret i32 [[R]]
|
||||
;
|
||||
%a = alloca {i32, i32}
|
||||
@ -59,7 +62,8 @@ define i32 @twostore() {
|
||||
; CHECK-NEXT: store i32 1, ptr [[A]], align 4
|
||||
; CHECK-NEXT: call void @callee(ptr [[A]])
|
||||
; CHECK-NEXT: store i32 2, ptr [[A]], align 4
|
||||
; CHECK-NEXT: ret i32 2
|
||||
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[A]], align 4
|
||||
; CHECK-NEXT: ret i32 [[L]]
|
||||
;
|
||||
%a = alloca i32
|
||||
store i32 1, ptr %a
|
||||
@ -112,8 +116,10 @@ define i32 @twocalls() {
|
||||
; CHECK-NEXT: [[B:%.*]] = getelementptr i32, ptr [[A]], i32 1
|
||||
; CHECK-NEXT: store i32 1, ptr [[B]], align 4
|
||||
; CHECK-NEXT: call void @callee(ptr [[A]])
|
||||
; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[A]], align 4
|
||||
; CHECK-NEXT: call void @callee(ptr [[A]])
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 0, 1
|
||||
; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[B]], align 4
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 [[L1]], [[L2]]
|
||||
; CHECK-NEXT: ret i32 [[R]]
|
||||
;
|
||||
%a = alloca {i32, i32}
|
||||
@ -159,7 +165,8 @@ define i32 @atomic() {
|
||||
; CHECK-NEXT: store i32 1, ptr [[B]], align 4
|
||||
; CHECK-NEXT: call void @callee(ptr [[A]])
|
||||
; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr [[A]] seq_cst, align 4
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 [[L1]], 1
|
||||
; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[B]], align 4
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 [[L1]], [[L2]]
|
||||
; CHECK-NEXT: ret i32 [[R]]
|
||||
;
|
||||
%a = alloca {i32, i32}
|
||||
@ -177,10 +184,12 @@ define i32 @notdominating() {
|
||||
; CHECK-LABEL: @notdominating(
|
||||
; CHECK-NEXT: [[A:%.*]] = alloca { i32, i32 }, align 8
|
||||
; CHECK-NEXT: [[B:%.*]] = getelementptr i32, ptr [[A]], i32 1
|
||||
; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[A]], align 4
|
||||
; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[B]], align 4
|
||||
; CHECK-NEXT: store i32 0, ptr [[A]], align 4
|
||||
; CHECK-NEXT: store i32 1, ptr [[B]], align 4
|
||||
; CHECK-NEXT: call void @callee(ptr [[A]])
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 undef, undef
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 [[L1]], [[L2]]
|
||||
; CHECK-NEXT: ret i32 [[R]]
|
||||
;
|
||||
%a = alloca {i32, i32}
|
||||
@ -226,7 +235,9 @@ define i32 @multiuse() {
|
||||
; CHECK-NEXT: [[B:%.*]] = getelementptr i32, ptr [[A]], i32 1
|
||||
; CHECK-NEXT: store i32 1, ptr [[B]], align 4
|
||||
; CHECK-NEXT: call void @callee_multiuse(ptr [[A]], ptr [[A]])
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 0, 1
|
||||
; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[A]], align 4
|
||||
; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[B]], align 4
|
||||
; CHECK-NEXT: [[R:%.*]] = add i32 [[L1]], [[L2]]
|
||||
; CHECK-NEXT: ret i32 [[R]]
|
||||
;
|
||||
%a = alloca {i32, i32}
|
||||
@ -285,7 +296,8 @@ define void @incompletestruct(i1 %b, i1 %c) {
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[LII:%.*]] = alloca [[STRUCT_LOADIMMEDIATEINFO:%.*]], align 4
|
||||
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[LII]])
|
||||
; CHECK-NEXT: [[BF_CLEAR4:%.*]] = and i32 undef, -262144
|
||||
; CHECK-NEXT: [[BF_LOAD:%.*]] = load i32, ptr [[LII]], align 4
|
||||
; CHECK-NEXT: [[BF_CLEAR4:%.*]] = and i32 [[BF_LOAD]], -262144
|
||||
; CHECK-NEXT: [[BF_SET5:%.*]] = select i1 [[B:%.*]], i32 196608, i32 131072
|
||||
; CHECK-NEXT: [[BF_SET12:%.*]] = or disjoint i32 [[BF_SET5]], [[BF_CLEAR4]]
|
||||
; CHECK-NEXT: store i32 [[BF_SET12]], ptr [[LII]], align 4
|
||||
@ -313,7 +325,8 @@ define void @incompletestruct_bb(i1 %b, i1 %c) {
|
||||
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
||||
; CHECK: if.then:
|
||||
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr nonnull [[LII]])
|
||||
; CHECK-NEXT: [[BF_CLEAR4:%.*]] = and i32 undef, -262144
|
||||
; CHECK-NEXT: [[BF_LOAD:%.*]] = load i32, ptr [[LII]], align 4
|
||||
; CHECK-NEXT: [[BF_CLEAR4:%.*]] = and i32 [[BF_LOAD]], -262144
|
||||
; CHECK-NEXT: [[BF_SET5:%.*]] = select i1 [[B:%.*]], i32 196608, i32 131072
|
||||
; CHECK-NEXT: [[BF_SET12:%.*]] = or disjoint i32 [[BF_SET5]], [[BF_CLEAR4]]
|
||||
; CHECK-NEXT: store i32 [[BF_SET12]], ptr [[LII]], align 4
|
||||
|
||||
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Reference in New Issue
Block a user