diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 4ae268679ca3..93d28d22bfd1 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -1199,6 +1199,7 @@ public: case AMDGPU::S_WAIT_EXPCNT: case AMDGPU::S_WAIT_DSCNT: case AMDGPU::S_WAIT_KMCNT: + case AMDGPU::S_WAIT_XCNT: case AMDGPU::S_WAIT_IDLE: return true; default: diff --git a/llvm/test/CodeGen/AMDGPU/insert-skips-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/insert-skips-gfx1250.mir new file mode 100644 index 000000000000..8a5d9cb6c563 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/insert-skips-gfx1250.mir @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass si-pre-emit-peephole -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: skip_wait_xcnt +body: | + ; CHECK-LABEL: name: skip_wait_xcnt + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: V_NOP_e32 implicit $exec + ; CHECK-NEXT: S_WAIT_XCNT 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1, %bb.2 + S_CBRANCH_EXECZ %bb.2, implicit $exec + + bb.1: + successors: %bb.2 + V_NOP_e32 implicit $exec + S_WAIT_XCNT 0 + + bb.2: + S_ENDPGM 0 +... + +--- +name: skip_wait_asynccnt +body: | + ; CHECK-LABEL: name: skip_wait_asynccnt + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: V_NOP_e32 implicit $exec + ; CHECK-NEXT: S_WAIT_ASYNCCNT 0, implicit $asynccnt, implicit-def $asynccnt + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1, %bb.2 + S_CBRANCH_EXECZ %bb.2, implicit $exec + + bb.1: + successors: %bb.2 + V_NOP_e32 implicit $exec + S_WAIT_ASYNCCNT 0, implicit $asynccnt, implicit-def $asynccnt + + bb.2: + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir b/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir index 60975d7a8d72..c5b7ebe0c78f 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir +++ b/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir @@ -84,3 +84,43 @@ body: | $vgpr260 = V_AND_B32_e32 496, $vgpr260, implicit $exec S_ENDPGM 0 ... + +--- +name: xcnt +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr10, $vgpr257 + ; CHECK-LABEL: name: xcnt + ; CHECK: liveins: $vgpr10, $vgpr257 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $vgpr11 = nofpexcept V_EXP_F32_e32 killed $vgpr10, implicit $mode, implicit $exec + ; CHECK-NEXT: S_SET_VGPR_MSB 65, implicit-def $mode + ; CHECK-NEXT: S_WAIT_XCNT 0 + ; CHECK-NEXT: $vgpr256 = nofpexcept V_EXP_F32_e32 killed $vgpr257, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0 + $vgpr11 = nofpexcept V_EXP_F32_e32 killed $vgpr10, implicit $mode, implicit $exec + S_WAIT_XCNT 0 + $vgpr256 = nofpexcept V_EXP_F32_e32 killed $vgpr257, implicit $mode, implicit $exec + S_ENDPGM 0 +... + +--- +name: asynccnt +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr10, $vgpr257 + ; CHECK-LABEL: name: asynccnt + ; CHECK: liveins: $vgpr10, $vgpr257 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $vgpr11 = nofpexcept V_EXP_F32_e32 killed $vgpr10, implicit $mode, implicit $exec + ; CHECK-NEXT: S_WAIT_ASYNCCNT 0, implicit $asynccnt, implicit-def $asynccnt + ; CHECK-NEXT: S_SET_VGPR_MSB 65, implicit-def $mode + ; CHECK-NEXT: $vgpr256 = nofpexcept V_EXP_F32_e32 killed $vgpr257, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0 + $vgpr11 = nofpexcept V_EXP_F32_e32 killed $vgpr10, implicit $mode, implicit $exec + S_WAIT_ASYNCCNT 0, implicit $asynccnt, implicit-def $asynccnt + $vgpr256 = nofpexcept V_EXP_F32_e32 killed $vgpr257, implicit $mode, implicit $exec + S_ENDPGM 0 +...