[AMDGPU] Apply alignment attr for make.buffer.rsrc (#166914)
Calculating alignment for `make.buffer.rsrc` intrinsic. The logic is the
alignment on use of return value of `make.buffer.rsrc` should be capped
by the base operand's alignment of `make.buffer.rsrc`.
For example:
```ll
define float @foo(ptr addrspace(1) align X %ptr) {
%fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) %ptr, i16 0, i32 C, i32 0)
%y = load float, ptr addrspace(7) %fat.ptr, align Y
ret float %y
}
```
We hopes that `Y = min(X, Y)`
---
After discussion, it seems improper for letting `Y = min(X, Y)` since it
contradict with the semantic of align on load.
So we would apply the origin behavior of align, which is letting `X` and
`Y` both equal to `max(X, Y)`
---------
Co-authored-by: Shilei Tian <i@tianshilei.me>
This commit is contained in:
Shoreshen
GitHub
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commit
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@ -1603,7 +1603,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
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&AAAMDGPUMinAGPRAlloc::ID, &AACallEdges::ID, &AAPointerInfo::ID,
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&AAPotentialConstantValues::ID, &AAUnderlyingObjects::ID,
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&AANoAliasAddrSpace::ID, &AAAddressSpace::ID, &AAIndirectCallInfo::ID,
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&AAAMDGPUClusterDims::ID});
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&AAAMDGPUClusterDims::ID, &AAAlign::ID});
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AttributorConfig AC(CGUpdater);
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AC.IsClosedWorldModule = Options.IsClosedWorld;
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@ -1661,6 +1661,10 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
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if (Ptr) {
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A.getOrCreateAAFor<AAAddressSpace>(IRPosition::value(*Ptr));
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A.getOrCreateAAFor<AANoAliasAddrSpace>(IRPosition::value(*Ptr));
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if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(Ptr)) {
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if (II->getIntrinsicID() == Intrinsic::amdgcn_make_buffer_rsrc)
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A.getOrCreateAAFor<AAAlign>(IRPosition::value(*Ptr));
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}
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}
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}
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}
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@ -5220,6 +5220,13 @@ static unsigned getKnownAlignForUse(Attributor &A, AAAlign &QueryingAA,
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return AlignAA->getKnownAlign().value();
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break;
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}
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case Intrinsic::amdgcn_make_buffer_rsrc: {
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const auto *AlignAA = A.getAAFor<AAAlign>(
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QueryingAA, IRPosition::value(*II), DepClassTy::NONE);
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if (AlignAA)
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return AlignAA->getKnownAlign().value();
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break;
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}
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default:
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break;
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}
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@ -5543,7 +5550,7 @@ struct AAAlignCallSiteReturned final
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const auto *AlignAA =
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A.getAAFor<AAAlign>(*this, IRPosition::value(*(II->getOperand(0))),
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DepClassTy::REQUIRED);
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if (AlignAA && AlignAA->isValidState()) {
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if (AlignAA) {
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Alignment = std::max(AlignAA->getAssumedAlign(), Alignment);
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Valid = true;
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}
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@ -5554,6 +5561,18 @@ struct AAAlignCallSiteReturned final
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std::min(this->getAssumedAlign(), Alignment).value());
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break;
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}
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// FIXME: Should introduce target specific sub-attributes and letting
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// getAAfor<AAAlign> lead to create sub-attribute to handle target
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// specific intrinsics.
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case Intrinsic::amdgcn_make_buffer_rsrc: {
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const auto *AlignAA =
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A.getAAFor<AAAlign>(*this, IRPosition::value(*(II->getOperand(0))),
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DepClassTy::REQUIRED);
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if (AlignAA)
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return clampStateAndIndicateChange<StateType>(
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this->getState(), AlignAA->getAssumedAlign().value());
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break;
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}
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default:
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break;
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}
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40
llvm/test/CodeGen/AMDGPU/attr-amdgpu-align.ll
Normal file
40
llvm/test/CodeGen/AMDGPU/attr-amdgpu-align.ll
Normal file
@ -0,0 +1,40 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s -o - | FileCheck %s
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define float @align_back_prop(ptr addrspace(1) align 4 %x) {
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; CHECK-LABEL: define float @align_back_prop(
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; CHECK-SAME: ptr addrspace(1) align 8 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[FAT_PTR:%.*]] = call align 8 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) [[X]], i16 0, i64 256, i32 0)
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; CHECK-NEXT: [[Y:%.*]] = load float, ptr addrspace(7) [[FAT_PTR]], align 8
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; CHECK-NEXT: ret float [[Y]]
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;
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%fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) %x, i16 0, i64 256, i32 0)
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%y = load float, ptr addrspace(7) %fat.ptr, align 8
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ret float %y
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}
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define float @align_foward_prop(ptr addrspace(1) align 8 %x) {
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; CHECK-LABEL: define float @align_foward_prop(
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; CHECK-SAME: ptr addrspace(1) align 8 [[X:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[FAT_PTR:%.*]] = call align 8 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) [[X]], i16 0, i64 256, i32 0)
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; CHECK-NEXT: [[Y:%.*]] = load float, ptr addrspace(7) [[FAT_PTR]], align 8
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; CHECK-NEXT: ret float [[Y]]
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;
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%fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) %x, i16 0, i64 256, i32 0)
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%y = load float, ptr addrspace(7) %fat.ptr, align 4
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ret float %y
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}
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define float @align_mix_prop(ptr addrspace(1) align 4 %x) {
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; CHECK-LABEL: define float @align_mix_prop(
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; CHECK-SAME: ptr addrspace(1) align 8 [[X:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[FAT_PTR:%.*]] = call align 8 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) [[X]], i16 0, i64 256, i32 0)
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; CHECK-NEXT: [[Y:%.*]] = load float, ptr addrspace(7) [[FAT_PTR]], align 8
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; CHECK-NEXT: [[Z:%.*]] = load float, ptr addrspace(1) [[X]], align 8
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; CHECK-NEXT: ret float [[Z]]
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;
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%fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) %x, i16 0, i64 256, i32 0)
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%y = load float, ptr addrspace(7) %fat.ptr, align 2
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%z = load float, ptr addrspace(1) %x, align 8
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ret float %z
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}
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@ -305,7 +305,7 @@ define amdgpu_kernel void @test_call_untouched_ptr() {
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define amdgpu_kernel void @test_make_buffer(ptr addrspace(1) %ptr) {
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; AMDGCN-LABEL: define amdgpu_kernel void @test_make_buffer(
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; AMDGCN-SAME: ptr addrspace(1) nofree readonly captures(none) [[PTR:%.*]]) #[[ATTR2]] {
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; AMDGCN-SAME: ptr addrspace(1) nofree readonly align 4 captures(none) [[PTR:%.*]]) #[[ATTR2]] {
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; AMDGCN-NEXT: [[RSRC:%.*]] = call align 4 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) [[PTR]], i16 noundef 0, i64 noundef 0, i32 noundef 0) #[[ATTR11:[0-9]+]]
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; AMDGCN-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(7) [[RSRC]], align 4
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; AMDGCN-NEXT: call void @clobber(i32 [[VAL]]) #[[ATTR7]]
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@ -320,7 +320,7 @@ define amdgpu_kernel void @test_make_buffer(ptr addrspace(1) %ptr) {
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define amdgpu_kernel void @test_make_buffer_noalias(ptr addrspace(1) noalias %ptr) {
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; AMDGCN-LABEL: define amdgpu_kernel void @test_make_buffer_noalias(
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; AMDGCN-SAME: ptr addrspace(1) noalias nofree readonly captures(none) [[PTR:%.*]]) #[[ATTR2]] {
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; AMDGCN-SAME: ptr addrspace(1) noalias nofree readonly align 4 captures(none) [[PTR:%.*]]) #[[ATTR2]] {
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; AMDGCN-NEXT: [[RSRC:%.*]] = call align 4 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) [[PTR]], i16 noundef 0, i64 noundef 0, i32 noundef 0) #[[ATTR11]]
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; AMDGCN-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(7) [[RSRC]], align 4, !invariant.load [[META0]]
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; AMDGCN-NEXT: call void @clobber(i32 [[VAL]]) #[[ATTR7]]
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