[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule (#142560)
The previous system explicitly enumerated the types. P0 was missing and thus we couldn't handle a select of P0s for example. Generalize the logic to simply check the width of the pointer for 32/64 bit pointers, this should handle all common address spaces
This commit is contained in:
Pierre van Houtryve
GitHub
parent
50a7511138
commit
e73bff89ef
@ -199,13 +199,11 @@ UniformityLLTOpPredicateID LLTToId(LLT Ty) {
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UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
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if (Ty == LLT::scalar(32) || Ty == LLT::fixed_vector(2, 16) ||
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Ty == LLT::pointer(3, 32) || Ty == LLT::pointer(5, 32) ||
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Ty == LLT::pointer(6, 32))
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(Ty.isPointer() && Ty.getSizeInBits() == 32))
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return B32;
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if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
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Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(1, 64) ||
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Ty == LLT::pointer(4, 64) ||
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(Ty.isPointer() && Ty.getAddressSpace() > AMDGPUAS::MAX_AMDGPU_ADDRESS))
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Ty == LLT::fixed_vector(4, 16) ||
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(Ty.isPointer() && Ty.getSizeInBits() == 64))
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return B64;
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if (Ty == LLT::fixed_vector(3, 32))
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return B96;
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@ -896,6 +896,31 @@ body: |
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%5:_(<4 x s16>) = G_SELECT %4, %2, %3
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...
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---
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name: select_p0_scc_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
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; CHECK-LABEL: name: select_p0_scc_ss
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; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(p0) = COPY $sgpr4_sgpr5
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[C]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(p0) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]]
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(p0) = COPY $sgpr2_sgpr3
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%3:_(p0) = COPY $sgpr4_sgpr5
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(p0) = G_SELECT %4, %2, %3
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...
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---
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name: select_p1_scc_ss
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legalized: true
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@ -946,6 +971,36 @@ body: |
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%5:_(p999) = G_SELECT %4, %2, %3
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...
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---
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name: select_p0_scc_sv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
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; CHECK-LABEL: name: select_p0_scc_sv
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; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY2]](p0)
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; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV]], [[UV2]]
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; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV1]], [[UV3]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(p0) = COPY $sgpr2_sgpr3
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%3:_(p0) = COPY $vgpr0_vgpr1
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(p0) = G_SELECT %4, %2, %3
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...
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---
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name: select_p1_scc_sv
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legalized: true
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@ -976,6 +1031,35 @@ body: |
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...
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---
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name: select_p0_scc_vs
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
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; CHECK-LABEL: name: select_p0_scc_vs
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; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY2]](p0)
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; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV]], [[UV2]]
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; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV1]], [[UV3]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(p0) = COPY $sgpr2_sgpr3
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%3:_(p0) = COPY $vgpr0_vgpr1
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(p0) = G_SELECT %4, %3, %2
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...
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---
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name: select_p1_scc_vs
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legalized: true
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@ -1033,6 +1117,35 @@ body: |
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%5:_(p1) = G_SELECT %4, %2, %3
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...
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---
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name: select_p0_vcc_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr0, $vgpr1
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; CHECK-LABEL: name: select_p0_vcc_ss
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; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY3]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(p0) = COPY [[COPY1]](p0)
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; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY5]](p0)
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
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; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
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%0:_(p0) = COPY $sgpr0_sgpr1
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%1:_(p0) = COPY $sgpr2_sgpr3
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%2:_(s32) = COPY $vgpr0
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%3:_(s32) = COPY $vgpr1
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%4:_(s1) = G_ICMP intpred(ne), %2, %3
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%5:_(p0) = G_SELECT %4, %0, %1
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...
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---
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name: select_p1_vcc_ss
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legalized: true
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@ -1062,6 +1175,34 @@ body: |
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%5:_(p1) = G_SELECT %4, %0, %1
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...
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---
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name: select_p0_vcc_sv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
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; CHECK-LABEL: name: select_p0_vcc_sv
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; CHECK: liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr2_vgpr3
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
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; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
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; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
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%0:_(p0) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(p0) = COPY $vgpr2_vgpr3
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%4:_(s1) = G_ICMP intpred(ne), %1, %2
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%5:_(p0) = G_SELECT %4, %0, %3
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...
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---
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name: select_p1_vcc_sv
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legalized: true
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@ -1090,6 +1231,34 @@ body: |
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%5:_(p1) = G_SELECT %4, %0, %3
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...
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---
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name: select_p0_vcc_vs
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
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; CHECK-LABEL: name: select_p0_vcc_vs
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; CHECK: liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr2_vgpr3
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
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; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
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; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
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%0:_(p0) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(p0) = COPY $vgpr2_vgpr3
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%4:_(s1) = G_ICMP intpred(ne), %1, %2
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%5:_(p0) = G_SELECT %4, %3, %0
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...
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---
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name: select_p1_vcc_vs
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legalized: true
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@ -1118,6 +1287,33 @@ body: |
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%5:_(p1) = G_SELECT %4, %3, %0
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...
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---
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name: select_p0_vcc_vv
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
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; CHECK-LABEL: name: select_p0_vcc_vv
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY $vgpr2_vgpr3
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr4_vgpr5
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p0)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
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; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(p0) = COPY $vgpr2_vgpr3
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%3:_(p0) = COPY $vgpr4_vgpr5
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(p0) = G_SELECT %4, %2, %3
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...
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---
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name: select_p1_vcc_vv
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legalized: true
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