diff --git a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
index ca774825f4dd..fa52b96e9ea9 100644
--- a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
+++ b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
@@ -1,19 +1,9 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
 # RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s
 
-# Check that coalescer does not create wider register tuple than in source
-
-# CHECK:  - { id: 2, class: vreg_64, preferred-register: '', flags: [  ] }
-# CHECK:  - { id: 3, class: vreg_64, preferred-register: '', flags: [  ] }
-# CHECK:  - { id: 4, class: vreg_64, preferred-register: '', flags: [  ] }
-# CHECK:  - { id: 5, class: vreg_96, preferred-register: '', flags: [  ] }
-# CHECK:  - { id: 6, class: vreg_96, preferred-register: '', flags: [  ] }
-# CHECK:  - { id: 7, class: vreg_128, preferred-register: '', flags: [  ] }
-# CHECK:  - { id: 8, class: vreg_128, preferred-register: '', flags: [  ] }
+# Check that coalescer does not create wider register tuple than in
+# source.
 # No more registers shall be defined
-# CHECK-NEXT: liveins:
-# CHECK:    FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4,
-# CHECK:    FLAT_STORE_DWORDX3 $vgpr0_vgpr1, %6,
-
 ---
 name:            main
 alignment:       1
@@ -52,6 +42,23 @@ body:             |
   bb.0.entry:
     liveins: $sgpr0, $vgpr0_vgpr1
 
+    ; CHECK-LABEL: name: main
+    ; CHECK: liveins: $sgpr0, $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $sgpr0
+    ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY [[DEF]].sub0
+    ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:vreg_64 = COPY [[COPY]].sub1
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:vreg_64 = COPY [[COPY]].sub0
+    ; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_96 = IMPLICIT_DEF
+    ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:vreg_96 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:vreg_96 = COPY [[DEF]].sub0
+    ; CHECK-NEXT: FLAT_STORE_DWORDX3 $vgpr0_vgpr1, [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr
+    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
+    ; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0_sub1_sub2:vreg_128 = COPY [[DEF2]]
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]].sub3:vreg_128 = COPY [[DEF]].sub0
+    ; CHECK-NEXT: FLAT_STORE_DWORDX4 $vgpr0_vgpr1, [[COPY3]], 0, 0, implicit $exec, implicit $flat_scr
     %3 = IMPLICIT_DEF
     undef %4.sub0 = COPY $sgpr0
     %4.sub1 = COPY %3.sub0