From e9a62c7698f1e9d813842f5d0682895800ecbd4d Mon Sep 17 00:00:00 2001 From: zGoldthorpe Date: Thu, 2 Apr 2026 08:48:54 -0600 Subject: [PATCH] [DAG] `computeKnownFPClass`: handle `ISD::FABS` (#190069) Use `KnownFPClass::fabs` to handle `ISD::FABS`. This case will help with updating #188356 to use `computeKnownFPClass`. --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 ++++++ llvm/test/CodeGen/AMDGPU/rsq.f64.ll | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 60b1fc6a5166..6eb8853550a1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -6094,6 +6094,12 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op, Known = KnownFPClass::bitcast(VT.getFltSemantics(), Bits); break; } + case ISD::FABS: { + Known = computeKnownFPClass(Op.getOperand(0), DemandedElts, + InterestedClasses, Depth + 1); + Known.fabs(); + break; + } default: if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN || Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) { diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll index 238cff87f2d5..05bdac942ba6 100644 --- a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll @@ -283,7 +283,7 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_fabs(double inreg %x) { ; SI-SDAG-IR-LABEL: s_rsq_f64_fabs: ; SI-SDAG-IR: ; %bb.0: ; SI-SDAG-IR-NEXT: v_rsq_f64_e64 v[0:1], |s[0:1]| -; SI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x260 +; SI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x240 ; SI-SDAG-IR-NEXT: s_and_b32 s2, s1, 0x7fffffff ; SI-SDAG-IR-NEXT: v_cmp_class_f64_e64 vcc, |s[0:1]|, v2 ; SI-SDAG-IR-NEXT: v_mov_b32_e32 v3, s2 @@ -325,7 +325,7 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_fabs(double inreg %x) { ; VI-SDAG-IR-LABEL: s_rsq_f64_fabs: ; VI-SDAG-IR: ; %bb.0: ; VI-SDAG-IR-NEXT: v_rsq_f64_e64 v[0:1], |s[0:1]| -; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x260 +; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x240 ; VI-SDAG-IR-NEXT: v_cmp_class_f64_e64 vcc, |s[0:1]|, v2 ; VI-SDAG-IR-NEXT: s_and_b32 s2, s1, 0x7fffffff ; VI-SDAG-IR-NEXT: v_mov_b32_e32 v3, s2 @@ -1311,7 +1311,7 @@ define double @v_rsq_f64_fabs(double %x) { ; SI-SDAG-IR: ; %bb.0: ; SI-SDAG-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-IR-NEXT: v_rsq_f64_e64 v[2:3], |v[0:1]| -; SI-SDAG-IR-NEXT: v_mov_b32_e32 v5, 0x260 +; SI-SDAG-IR-NEXT: v_mov_b32_e32 v5, 0x240 ; SI-SDAG-IR-NEXT: v_cmp_class_f64_e64 vcc, |v[0:1]|, v5 ; SI-SDAG-IR-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1 ; SI-SDAG-IR-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc @@ -1347,7 +1347,7 @@ define double @v_rsq_f64_fabs(double %x) { ; VI-SDAG-IR: ; %bb.0: ; VI-SDAG-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-SDAG-IR-NEXT: v_rsq_f64_e64 v[2:3], |v[0:1]| -; VI-SDAG-IR-NEXT: v_mov_b32_e32 v4, 0x260 +; VI-SDAG-IR-NEXT: v_mov_b32_e32 v4, 0x240 ; VI-SDAG-IR-NEXT: v_cmp_class_f64_e64 vcc, |v[0:1]|, v4 ; VI-SDAG-IR-NEXT: v_and_b32_e32 v5, 0x7fffffff, v1 ; VI-SDAG-IR-NEXT: s_mov_b32 s4, 0