From ea251669ba3ff16ad459358287f7c273c28e0f8d Mon Sep 17 00:00:00 2001 From: Wei Xiao Date: Fri, 30 Jan 2026 02:37:49 +0800 Subject: [PATCH] [CodeGen] Fix MachineMemOperand Size of MaskedLoad (#156398) Fix MIR printing unknown-size issue of MaskedLoad. --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/test/CodeGen/X86/masked_expandload_isel.ll | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index d91dcc9105da..52e0d8fefdf2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5099,7 +5099,7 @@ void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( MachinePointerInfo(PtrOperand), MMOFlags, - LocationSize::beforeOrAfterPointer(), Alignment, AAInfo, Ranges); + VT.getStoreSize(), Alignment, AAInfo, Ranges); const auto &TLI = DAG.getTargetLoweringInfo(); diff --git a/llvm/test/CodeGen/X86/masked_expandload_isel.ll b/llvm/test/CodeGen/X86/masked_expandload_isel.ll index a153def4a71a..72323bc2d28b 100644 --- a/llvm/test/CodeGen/X86/masked_expandload_isel.ll +++ b/llvm/test/CodeGen/X86/masked_expandload_isel.ll @@ -10,7 +10,7 @@ define <8 x i16> @_Z3fooiPiPs(<8 x i16> %src, <8 x i1> %mask) #0 { ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm0 ; CHECK-NEXT: [[VPSLLWZ128ri:%[0-9]+]]:vr128x = VPSLLWZ128ri [[COPY]], 15 ; CHECK-NEXT: [[VPMOVW2MZ128kr:%[0-9]+]]:vk16wm = VPMOVW2MZ128kr killed [[VPSLLWZ128ri]] - ; CHECK-NEXT: [[VPEXPANDWZ128rmk:%[0-9]+]]:vr128x = VPEXPANDWZ128rmk [[COPY1]], killed [[VPMOVW2MZ128kr]], $noreg, 1, $noreg, 0, $noreg :: (load unknown-size from `ptr null`, align 1) + ; CHECK-NEXT: [[VPEXPANDWZ128rmk:%[0-9]+]]:vr128x = VPEXPANDWZ128rmk [[COPY1]], killed [[VPMOVW2MZ128kr]], $noreg, 1, $noreg, 0, $noreg :: (load (s128) from `ptr null`, align 1) ; CHECK-NEXT: $xmm0 = COPY [[VPEXPANDWZ128rmk]] ; CHECK-NEXT: RET 0, $xmm0 entry: @@ -27,7 +27,7 @@ define <8 x i16> @_Z3foo2iPiPs(<8 x i16> %src, <8 x i1> %mask) #0 { ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm0 ; CHECK-NEXT: [[VPSLLWZ128ri:%[0-9]+]]:vr128x = VPSLLWZ128ri [[COPY]], 15 ; CHECK-NEXT: [[VPMOVW2MZ128kr:%[0-9]+]]:vk16wm = VPMOVW2MZ128kr killed [[VPSLLWZ128ri]] - ; CHECK-NEXT: [[VPEXPANDWZ128rmk:%[0-9]+]]:vr128x = VPEXPANDWZ128rmk [[COPY1]], killed [[VPMOVW2MZ128kr]], $noreg, 1, $noreg, 0, $noreg :: (load unknown-size from `ptr null`, align 16) + ; CHECK-NEXT: [[VPEXPANDWZ128rmk:%[0-9]+]]:vr128x = VPEXPANDWZ128rmk [[COPY1]], killed [[VPMOVW2MZ128kr]], $noreg, 1, $noreg, 0, $noreg :: (load (s128) from `ptr null`) ; CHECK-NEXT: $xmm0 = COPY [[VPEXPANDWZ128rmk]] ; CHECK-NEXT: RET 0, $xmm0 entry: