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[Xtensa] Implement sextload i8 (#106053)

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Andrei Safronov 2024-08-26 18:21:34 +03:00 committed by GitHub
parent 0e24c32a6d
commit ea625f48ab
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2 changed files with 14 additions and 1 deletions
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3
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
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@ -70,11 +70,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
// No sign extend instructions for i1
// No sign extend instructions for i1 and sign extend load i8
for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}
setOperationAction(ISD::ConstantPool, PtrVT, Custom);

12
llvm/test/CodeGen/Xtensa/load.ll Normal file
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@ -0,0 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=xtensa < %s | FileCheck %s
define signext i8 @test_load_i8(ptr %p){
; CHECK-LABEL: test_load_i8:
; CHECK: l8ui a8, a2, 0
; CHECK-NEXT: slli a8, a8, 24
; CHECK-NEXT: srai a2, a8, 24
; CHECK-NEXT: ret
%1 = load i8, ptr %p, align 1
ret i8 %1
}