This reverts commit 9cc98e336980f00cbafcbed8841344e6ac472bdc. Issue: https://github.com/ClangBuiltLinux/linux/issues/1997
This commit is contained in:
Prabhuk
GitHub
parent
4bb0ca655b
commit
ea9ec80b7a
@ -356,8 +356,6 @@ def warn_target_unrecognized_env : Warning<
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def warn_knl_knm_isa_support_removed : Warning<
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"KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.">,
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InGroup<DiagGroup<"knl-knm-isa-support-removed">>;
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def err_target_unsupported_abi_with_fpu : Error<
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"'%0' ABI is not supported with FPU">;
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// Source manager
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def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
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@ -11314,8 +11314,6 @@ def err_omp_wrong_dependency_iterator_type : Error<
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def err_target_unsupported_type
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: Error<"%0 requires %select{|%2 bit size}1 %3 %select{|return }4type support,"
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" but target '%5' does not support it">;
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def err_target_unsupported_type_for_abi
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: Error<"%0 requires %1 type support, but ABI '%2' does not support it">;
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def err_omp_lambda_capture_in_declare_target_not_to : Error<
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"variable captured in declare target region must appear in a to clause">;
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def err_omp_device_type_mismatch : Error<
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@ -231,7 +231,6 @@ protected:
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bool HasIbm128;
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bool HasLongDouble;
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bool HasFPReturn;
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bool HasFPTypes;
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bool HasStrictFP;
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unsigned char MaxAtomicPromoteWidth, MaxAtomicInlineWidth;
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@ -690,9 +689,6 @@ public:
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/// on this target.
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virtual bool hasFPReturn() const { return HasFPReturn; }
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/// Determine whether floating point types are supported for this target.
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virtual bool hasFPTypes() const { return HasFPTypes; }
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/// Determine whether constrained floating point is supported on this target.
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virtual bool hasStrictFP() const { return HasStrictFP; }
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@ -1335,10 +1331,6 @@ public:
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return false;
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}
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/// Make changes to the supported types which depend on both the target
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/// features and ABI.
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virtual void setSupportedArgTypes() {}
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/// Use the specified unit for FP math.
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///
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/// \return False on error (invalid unit name).
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@ -67,7 +67,6 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : Triple(T) {
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HasFullBFloat16 = false;
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HasLongDouble = true;
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HasFPReturn = true;
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HasFPTypes = true;
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HasStrictFP = false;
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PointerWidth = PointerAlign = 32;
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BoolWidth = BoolAlign = 8;
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@ -830,7 +830,6 @@ TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
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Target->setSupportedOpenCLOpts();
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Target->setCommandLineOpenCLOpts();
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Target->setMaxAtomicWidth();
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Target->setSupportedArgTypes();
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if (!Opts->DarwinTargetVariantTriple.empty())
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Target->DarwinTargetVariantTriple =
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@ -11,7 +11,6 @@
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "clang/Basic/Diagnostic.h"
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#include "clang/Basic/LangOptions.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "clang/Basic/TargetInfo.h"
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@ -200,32 +199,13 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
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StringRef AArch64TargetInfo::getABI() const { return ABI; }
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bool AArch64TargetInfo::setABI(const std::string &Name) {
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if (Name != "aapcs" && Name != "aapcs-soft" && Name != "darwinpcs")
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if (Name != "aapcs" && Name != "darwinpcs")
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return false;
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ABI = Name;
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return true;
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}
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void AArch64TargetInfo::setSupportedArgTypes() {
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if (!(FPU & FPUMode) && ABI != "aapcs-soft") {
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// When a hard-float ABI is used on a target without an FPU, all
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// floating-point argument and return types are rejected because they must
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// be passed in FP registers.
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HasFPTypes = false;
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}
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}
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bool AArch64TargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
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if (hasFeature("fp") && ABI == "aapcs-soft") {
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// aapcs-soft is not allowed for targets with an FPU, to avoid there being
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// two incomatible ABIs.
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Diags.Report(diag::err_target_unsupported_abi_with_fpu) << ABI;
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return false;
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}
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return true;
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}
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bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef,
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BranchProtectionInfo &BPI,
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StringRef &Err) const {
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@ -706,8 +686,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
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return llvm::StringSwitch<bool>(Feature)
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.Cases("aarch64", "arm64", "arm", true)
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.Case("fmv", HasFMV)
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.Case("fp", FPU & FPUMode)
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.Cases("neon", "simd", FPU & NeonMode)
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.Cases("neon", "fp", "simd", FPU & NeonMode)
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.Case("jscvt", HasJSCVT)
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.Case("fcma", HasFCMA)
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.Case("rng", HasRandGen)
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@ -96,7 +96,6 @@ public:
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StringRef getABI() const override;
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bool setABI(const std::string &Name) override;
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void setSupportedArgTypes() override;
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bool validateBranchProtection(StringRef Spec, StringRef Arch,
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BranchProtectionInfo &BPI,
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@ -200,8 +199,6 @@ public:
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bool hasInt128Type() const override;
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bool hasBitIntType() const override { return true; }
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bool validateTarget(DiagnosticsEngine &Diags) const override;
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};
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class LLVM_LIBRARY_VISIBILITY AArch64leTargetInfo : public AArch64TargetInfo {
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@ -145,8 +145,6 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
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Kind = AArch64ABIKind::DarwinPCS;
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else if (Triple.isOSWindows())
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return createWindowsAArch64TargetCodeGenInfo(CGM, AArch64ABIKind::Win64);
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else if (Target.getABI() == "aapcs-soft")
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Kind = AArch64ABIKind::AAPCSSoft;
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return createAArch64TargetCodeGenInfo(CGM, Kind);
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}
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@ -416,7 +416,6 @@ enum class AArch64ABIKind {
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AAPCS = 0,
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DarwinPCS,
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Win64,
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AAPCSSoft,
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};
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std::unique_ptr<TargetCodeGenInfo>
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@ -53,8 +53,8 @@ private:
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Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
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CodeGenFunction &CGF) const;
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Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty, CodeGenFunction &CGF,
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AArch64ABIKind Kind) const;
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Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
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CodeGenFunction &CGF) const;
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Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
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QualType Ty) const override {
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@ -65,7 +65,7 @@ private:
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return Kind == AArch64ABIKind::Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
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: isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
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: EmitAAPCSVAArg(VAListAddr, Ty, CGF, Kind);
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: EmitAAPCSVAArg(VAListAddr, Ty, CGF);
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}
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Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
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@ -482,11 +482,6 @@ bool AArch64SwiftABIInfo::isLegalVectorType(CharUnits VectorSize,
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}
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bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
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// For the soft-float ABI variant, no types are considered to be homogeneous
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// aggregates.
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if (Kind == AArch64ABIKind::AAPCSSoft)
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return false;
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// Homogeneous aggregates for AAPCS64 must have base types of a floating
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// point type or a short-vector type. This is the same as the 32-bit ABI,
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// but with the difference that any floating-point type is allowed,
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@ -518,8 +513,7 @@ bool AArch64ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate()
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}
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Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
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CodeGenFunction &CGF,
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AArch64ABIKind Kind) const {
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CodeGenFunction &CGF) const {
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ABIArgInfo AI = classifyArgumentType(Ty, /*IsVariadic=*/true,
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CGF.CurFnInfo->getCallingConvention());
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// Empty records are ignored for parameter passing purposes.
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@ -544,8 +538,7 @@ Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
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BaseTy = ArrTy->getElementType();
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NumRegs = ArrTy->getNumElements();
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}
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bool IsFPR = Kind != AArch64ABIKind::AAPCSSoft &&
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(BaseTy->isFloatingPointTy() || BaseTy->isVectorTy());
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bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
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// The AArch64 va_list type and handling is specified in the Procedure Call
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// Standard, section B.4:
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@ -1944,21 +1944,6 @@ Sema::SemaDiagnosticBuilder Sema::Diag(SourceLocation Loc, unsigned DiagID,
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return DB;
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}
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static bool typeIsOrContainsFloat(const Type &Ty) {
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if (Ty.isFloatingType())
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return true;
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if (const RecordDecl *Decl = Ty.getAsRecordDecl()) {
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for (const FieldDecl *FD : Decl->fields()) {
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const Type &FieldType = *FD->getType();
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if (typeIsOrContainsFloat(FieldType))
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return true;
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}
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}
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return false;
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}
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void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
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if (isUnevaluatedContext() || Ty.isNull())
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return;
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@ -2103,25 +2088,6 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
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!Builtin::evaluateRequiredTargetFeatures("sme", CallerFeatureMap))
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Diag(D->getLocation(), diag::err_sve_vector_in_non_sve_target) << Ty;
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}
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// Don't allow any floating-point types (including structs containing
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// floats) for ABIs which do not support them.
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if (!TI.hasFPTypes() && typeIsOrContainsFloat(*UnqualTy)) {
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PartialDiagnostic PD = PDiag(diag::err_target_unsupported_type_for_abi);
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if (D)
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PD << D;
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else
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PD << "expression";
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if (Diag(Loc, PD, FD) << Ty << TI.getABI()) {
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if (D)
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D->setInvalidDecl();
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}
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if (D)
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targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
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}
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};
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CheckType(Ty);
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@ -1,56 +0,0 @@
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// RUN: %clang_cc1 -triple aarch64 -target-feature +fp-armv8 -target-abi aapcs -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD
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// RUN: %clang_cc1 -triple aarch64 -target-feature -fp-armv8 -target-abi aapcs-soft -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,SOFT
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// See also llvm/test/CodeGen/AArch64/soft-float-abi.ll, which checks the LLVM
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// backend parts of the soft-float ABI.
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// The va_list type does not change between the ABIs
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// CHECK: %struct.__va_list = type { ptr, ptr, ptr, i32, i32 }
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// Floats are passed in integer registers, this will be handled by the backend.
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// CHECK: define dso_local half @test0(half noundef %a)
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// CHECK: define dso_local bfloat @test1(bfloat noundef %a)
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// CHECK: define dso_local float @test2(float noundef %a)
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// CHECK: define dso_local double @test3(double noundef %a)
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// CHECK: define dso_local fp128 @test4(fp128 noundef %a)
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__fp16 test0(__fp16 a) { return a; }
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__bf16 test1(__bf16 a) { return a; }
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float test2(float a) { return a; }
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double test3(double a) { return a; }
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long double test4(long double a) { return a; }
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// No types are considered to be HFAs or HVAs by the soft-float PCS, so these
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// are converted to integer types.
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struct A {
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float x;
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};
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// SOFT: define dso_local i32 @test10(i64 %a.coerce)
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// HARD: define dso_local %struct.A @test10([1 x float] alignstack(8) %a.coerce)
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struct A test10(struct A a) { return a; }
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struct B {
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double x;
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double y;
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};
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// SOFT: define dso_local [2 x i64] @test11([2 x i64] %a.coerce)
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// HARD: define dso_local %struct.B @test11([2 x double] alignstack(8) %a.coerce)
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struct B test11(struct B a) { return a; }
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#include <stdarg.h>
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// For variadic arguments, va_arg will always retreive
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// CHECK-LABEL: define dso_local double @test20(i32 noundef %a, ...)
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// CHECK: %vl = alloca %struct.__va_list, align 8
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// SOFT: %gr_offs_p = getelementptr inbounds %struct.__va_list, ptr %vl, i32 0, i32 3
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// SOFT: %reg_top_p = getelementptr inbounds %struct.__va_list, ptr %vl, i32 0, i32 1
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// HARD: %vr_offs_p = getelementptr inbounds %struct.__va_list, ptr %vl, i32 0, i32 4
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// HARD: %reg_top_p = getelementptr inbounds %struct.__va_list, ptr %vl, i32 0, i32 2
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double test20(int a, ...) {
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va_list vl;
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va_start(vl, a);
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return va_arg(vl, double);
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}
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// Vector types are only available for targets with the correct hardware, and
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// their calling-convention is left undefined by the soft-float ABI, so they
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// aren't tested here.
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@ -1,6 +1,6 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-attributes --check-globals --include-generated-funcs
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8 -S -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8 -target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -S -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
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int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
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int __attribute__((target_clones("sha2", "sha2+memtag2", " default "))) ftc_def(void) { return 1; }
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@ -414,23 +414,23 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK-NOFMV-NEXT: ret i32 [[ADD5]]
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//
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//.
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// CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,-fp-armv8" }
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// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,-fp-armv8" }
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// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8" }
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// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+sha2,-fp-armv8" }
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// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mte,+neon,+sha2,-fp-armv8" }
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// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp-armv8" }
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// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+neon,-fp-armv8" }
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// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rand,-fp-armv8" }
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// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc,-fp-armv8" }
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// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt,-fp-armv8" }
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// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,-fp-armv8" }
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// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm,-fp-armv8" }
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// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,-fp-armv8" }
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// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sb,+sve,-fp-armv8" }
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// CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" }
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// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" }
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// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sha2" }
|
||||
// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" }
|
||||
// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
|
||||
// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" }
|
||||
// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" }
|
||||
// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" }
|
||||
// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
|
||||
// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
|
||||
// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" }
|
||||
// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" }
|
||||
// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" }
|
||||
//.
|
||||
// CHECK-NOFMV: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv,-fp-armv8" }
|
||||
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv,-fp-armv8" }
|
||||
// CHECK-NOFMV: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
|
||||
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
|
||||
//.
|
||||
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
|
||||
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
|
||||
|
||||
@ -1,25 +0,0 @@
|
||||
// REQUIRES: aarch64-registered-target
|
||||
|
||||
// Hard-float, valid
|
||||
// RUN: %clang --target=aarch64-none-elf -c %s -o /dev/null
|
||||
// RUN: %clang --target=aarch64-none-elf -mabi=aapcs -c %s -o /dev/null
|
||||
// RUN: %clang --target=aarch64-none-elf -march=armv8-r -c %s -o /dev/null
|
||||
// RUN: %clang --target=aarch64-none-elf -march=armv8-r -mabi=aapcs -c %s -o /dev/null
|
||||
// RUN: %clang --target=aarch64-none-elf -march=armv8-r+fp -mabi=aapcs -c %s -o /dev/null
|
||||
|
||||
// Soft-float, no FP
|
||||
// RUN: %clang --target=aarch64-none-elf -march=armv8-r+nofp -mabi=aapcs-soft -c %s -o /dev/null
|
||||
// RUN: %clang --target=aarch64-none-elf -mgeneral-regs-only -mabi=aapcs-soft -c %s -o /dev/null
|
||||
|
||||
// Soft-float, FP hardware: Rejected, to avoid having two incompatible ABIs for common targets.
|
||||
// RUN: not %clang --target=aarch64-none-elf -mabi=aapcs-soft -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=INVALID-SOFT
|
||||
// RUN: not %clang --target=aarch64-none-elf -march=armv8-r+fp -mabi=aapcs-soft -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=INVALID-SOFT
|
||||
// RUN: not %clang --target=aarch64-none-elf -march=armv8-r+nofp+fp -mabi=aapcs-soft -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=INVALID-SOFT
|
||||
|
||||
// No FP, hard-float. This is accepted by the driver, but any use of
|
||||
// floating-point types will be rejected by Sema (tested elsewhere).
|
||||
// RUN: %clang --target=aarch64-none-elf -march=armv8-r+nofp -c %s -o /dev/null
|
||||
// RUN: %clang --target=aarch64-none-elf -march=armv8-r+nofp -mabi=aapcs -c %s -o /dev/null
|
||||
// RUN: %clang --target=aarch64-none-elf -mgeneral-regs-only -mabi=aapcs -c %s -o /dev/null
|
||||
|
||||
// INVALID-SOFT: error: 'aapcs-soft' ABI is not supported with FPU
|
||||
@ -342,15 +342,15 @@
|
||||
|
||||
// RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
|
||||
// RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
|
||||
// RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto -mabi=aapcs-soft -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s
|
||||
// RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto+nofp+nosimd+nocrc+nocrypto -mabi=aapcs-soft -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s
|
||||
// RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s
|
||||
// RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto+nofp+nosimd+nocrc+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s
|
||||
// RUN: %clang -target aarch64 -march=armv8-a+nosimd -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-3 %s
|
||||
// CHECK-MARCH-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
|
||||
// CHECK-MARCH-2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-fp-armv8"{{.*}} "-target-feature" "-neon"
|
||||
// CHECK-MARCH-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-neon"
|
||||
|
||||
// While we're checking +nofp, also make sure it stops defining __ARM_FP
|
||||
// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-r+nofp -mabi=aapcs-soft -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-NOFP %s
|
||||
// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-r+nofp -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-NOFP %s
|
||||
// CHECK-NOFP-NOT: #define __ARM_FP{{ }}
|
||||
|
||||
// Check +sm4:
|
||||
|
||||
@ -1,54 +0,0 @@
|
||||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +fp-armv8 -fsyntax-only -target-abi aapcs -verify=fp-hard %s
|
||||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8 -fsyntax-only -target-abi aapcs-soft -verify=nofp-soft %s
|
||||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8 -fsyntax-only -target-abi aapcs -verify=nofp-hard %s
|
||||
// No run line needed for soft-float ABI with an FPU because that is rejected by the driver
|
||||
|
||||
// With the hard-float ABI and a target with an FPU, FP arguments are passed in
|
||||
// FP registers, no diagnostics needed.
|
||||
// fp-hard-no-diagnostics
|
||||
|
||||
// With the soft-float ABI, FP arguments are passed in integer registers, no
|
||||
// diagnostics needed.
|
||||
// nofp-soft-no-diagnostics
|
||||
|
||||
// With the hard-float ABI but no FPU, FP arguments cannot be passed in an
|
||||
// ABI-compatible way, so we report errors for these cases:
|
||||
|
||||
struct HFA {
|
||||
float x, y;
|
||||
};
|
||||
|
||||
struct non_HFA {
|
||||
float x;
|
||||
int y;
|
||||
};
|
||||
|
||||
float test_float_ret(void) { return 3.141f; } // #1
|
||||
// nofp-hard-error@#1 {{'test_float_ret' requires 'float' type support, but ABI 'aapcs' does not support it}}
|
||||
// nofp-hard-note@#1 {{'test_float_ret' defined here}}
|
||||
|
||||
struct HFA test_hfa_ret(void) { return (struct HFA){}; } // #2
|
||||
// nofp-hard-error@#2 {{'test_hfa_ret' requires 'struct HFA' type support, but ABI 'aapcs' does not support it}}
|
||||
// nofp-hard-note@#2 {{'test_hfa_ret' defined here}}
|
||||
|
||||
struct non_HFA test_non_hfa_ret(void) { return (struct non_HFA){}; } // #3
|
||||
// nofp-hard-error@#3 {{'test_non_hfa_ret' requires 'struct non_HFA' type support, but ABI 'aapcs' does not support it}}
|
||||
// nofp-hard-note@#3 {{'test_non_hfa_ret' defined here}}
|
||||
|
||||
void test_float_arg(float a) {} // #4
|
||||
// nofp-hard-error@#4 {{'test_float_arg' requires 'float' type support, but ABI 'aapcs' does not support it}}
|
||||
// nofp-hard-note@#4 {{'test_float_arg' defined here}}
|
||||
|
||||
void test_hfa_arg(struct HFA a) {} // #5
|
||||
// nofp-hard-error@#5 {{'test_hfa_arg' requires 'struct HFA' type support, but ABI 'aapcs' does not support it}}
|
||||
// nofp-hard-note@#5 {{'test_hfa_arg' defined here}}
|
||||
|
||||
void test_non_hfa_arg(struct non_HFA a) {} // #6
|
||||
// nofp-hard-error@#6 {{'test_non_hfa_arg' requires 'struct non_HFA' type support, but ABI 'aapcs' does not support it}}
|
||||
// nofp-hard-note@#6 {{'test_non_hfa_arg' defined here}}
|
||||
|
||||
int test_expr_float(int a) { return a + 1.0f; } // #7
|
||||
// nofp-hard-error@#7 {{expression requires 'float' type support, but ABI 'aapcs' does not support it}}
|
||||
|
||||
int test_expr_double(int a) { return a + 1.0; } // #8
|
||||
// nofp-hard-error@#8 {{expression requires 'double' type support, but ABI 'aapcs' does not support it}}
|
||||
@ -1,161 +0,0 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
|
||||
; RUN: llc --mtriple aarch64-none-eabi < %s -mattr=-fp-armv8 | FileCheck %s
|
||||
|
||||
; See also clang/test/CodeGen/aarch64-soft-float-abi.c, which tests the clang
|
||||
; parts of the soft-float ABI.
|
||||
|
||||
; FP types up to 64-bit are passed in a general purpose register.
|
||||
define half @test0(half %a, half %b) {
|
||||
; CHECK-LABEL: test0:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov w0, w1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
ret half %b
|
||||
}
|
||||
|
||||
define bfloat @test1(i32 %a, bfloat %b) {
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov w0, w1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
ret bfloat %b
|
||||
}
|
||||
|
||||
define float @test2(i64 %a, float %b) {
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov w0, w1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
ret float %b
|
||||
}
|
||||
|
||||
define double @test3(half %a, double %b) {
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov x0, x1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
ret double %b
|
||||
}
|
||||
|
||||
; fp128 is passed in a pair of GPRs.
|
||||
define fp128 @test4(fp128 %a, fp128 %b) {
|
||||
; CHECK-LABEL: test4:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov x1, x3
|
||||
; CHECK-NEXT: mov x0, x2
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
; fp128 is passed in an aligned pair of GPRs, leaving one register unused is
|
||||
; necessary.
|
||||
define fp128 @test5(float %a, fp128 %b) {
|
||||
; CHECK-LABEL: test5:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov x1, x3
|
||||
; CHECK-NEXT: mov x0, x2
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
; If the alignment of an fp128 leaves a register unused, it remains unused even
|
||||
; if a later argument could fit in it.
|
||||
define i64 @test6(i64 %a, fp128 %b, i64 %c) {
|
||||
; CHECK-LABEL: test6:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov x0, x4
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
ret i64 %c
|
||||
}
|
||||
|
||||
; HFAs are all bit-casted to integer types in the frontend when using the
|
||||
; soft-float ABI, so they get passed in the same way as non-homeogeneous
|
||||
; aggregates. The IR is identical to the equivalent integer types, so nothing
|
||||
; to test here.
|
||||
|
||||
; The PCS for vector and HVA types is not defined by the soft-float ABI because
|
||||
; these types are only defined by the ACLE when vector hardware is available,
|
||||
; so nothing to test here.
|
||||
|
||||
; The front-end generates IR for va_arg which always reads from the integer
|
||||
; register save area, and never the floating-point register save area. The
|
||||
; layout of the va_list type remains the same, the floating-point related
|
||||
; fields are unused. The only change needed in the backend is in va_start, to
|
||||
; not attempt to save the floating-point registers or set the FP fields in the
|
||||
; va_list.
|
||||
%struct.__va_list = type { ptr, ptr, ptr, i32, i32 }
|
||||
declare void @llvm.va_start(ptr)
|
||||
define double @test20(i32 %a, ...) {
|
||||
; CHECK-LABEL: test20:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: sub sp, sp, #96
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 96
|
||||
; CHECK-NEXT: mov w8, #-56 // =0xffffffc8
|
||||
; CHECK-NEXT: add x10, sp, #8
|
||||
; CHECK-NEXT: add x9, sp, #96
|
||||
; CHECK-NEXT: str x8, [sp, #88]
|
||||
; CHECK-NEXT: add x10, x10, #56
|
||||
; CHECK-NEXT: ldrsw x8, [sp, #88]
|
||||
; CHECK-NEXT: stp x1, x2, [sp, #8]
|
||||
; CHECK-NEXT: stp x3, x4, [sp, #24]
|
||||
; CHECK-NEXT: stp x5, x6, [sp, #40]
|
||||
; CHECK-NEXT: stp x7, x9, [sp, #56]
|
||||
; CHECK-NEXT: str x10, [sp, #72]
|
||||
; CHECK-NEXT: tbz w8, #31, .LBB7_3
|
||||
; CHECK-NEXT: // %bb.1: // %vaarg.maybe_reg
|
||||
; CHECK-NEXT: add w9, w8, #8
|
||||
; CHECK-NEXT: cmn w8, #8
|
||||
; CHECK-NEXT: str w9, [sp, #88]
|
||||
; CHECK-NEXT: b.gt .LBB7_3
|
||||
; CHECK-NEXT: // %bb.2: // %vaarg.in_reg
|
||||
; CHECK-NEXT: ldr x9, [sp, #72]
|
||||
; CHECK-NEXT: add x8, x9, x8
|
||||
; CHECK-NEXT: b .LBB7_4
|
||||
; CHECK-NEXT: .LBB7_3: // %vaarg.on_stack
|
||||
; CHECK-NEXT: ldr x8, [sp, #64]
|
||||
; CHECK-NEXT: add x9, x8, #8
|
||||
; CHECK-NEXT: str x9, [sp, #64]
|
||||
; CHECK-NEXT: .LBB7_4: // %vaarg.end
|
||||
; CHECK-NEXT: ldr x0, [x8]
|
||||
; CHECK-NEXT: add sp, sp, #96
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%vl = alloca %struct.__va_list, align 8
|
||||
call void @llvm.va_start(ptr nonnull %vl)
|
||||
%gr_offs_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 3
|
||||
%gr_offs = load i32, ptr %gr_offs_p, align 8
|
||||
%0 = icmp sgt i32 %gr_offs, -1
|
||||
br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg
|
||||
|
||||
vaarg.maybe_reg: ; preds = %entry
|
||||
%new_reg_offs = add nsw i32 %gr_offs, 8
|
||||
store i32 %new_reg_offs, ptr %gr_offs_p, align 8
|
||||
%inreg = icmp slt i32 %gr_offs, -7
|
||||
br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack
|
||||
|
||||
vaarg.in_reg: ; preds = %vaarg.maybe_reg
|
||||
%reg_top_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 1
|
||||
%reg_top = load ptr, ptr %reg_top_p, align 8
|
||||
%1 = sext i32 %gr_offs to i64
|
||||
%2 = getelementptr inbounds i8, ptr %reg_top, i64 %1
|
||||
br label %vaarg.end
|
||||
|
||||
vaarg.on_stack: ; preds = %vaarg.maybe_reg, %entry
|
||||
%stack = load ptr, ptr %vl, align 8
|
||||
%new_stack = getelementptr inbounds i8, ptr %stack, i64 8
|
||||
store ptr %new_stack, ptr %vl, align 8
|
||||
br label %vaarg.end
|
||||
|
||||
vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
|
||||
%vaargs.addr = phi ptr [ %2, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]
|
||||
%3 = load double, ptr %vaargs.addr, align 8
|
||||
ret double %3
|
||||
}
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user