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DAG: Fix arith_fence handling in SignBitIsZeroFP (#172537)

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Matt Arsenault 2025-12-16 21:10:38 +01:00 committed by GitHub
parent c956ac300d
commit eb1876c960
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2 changed files with 3 additions and 5 deletions
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2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -2807,7 +2807,7 @@ bool SelectionDAG::SignBitIsZeroFP(SDValue Op, unsigned Depth) const {
return (NoFPClass & TestMask) == TestMask;
}
case ISD::ARITH_FENCE:
return SignBitIsZeroFP(Op, Depth + 1);
return SignBitIsZeroFP(Op.getOperand(0), Depth + 1);
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FEXP10:

6
llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
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@ -184,11 +184,9 @@ define float @copysign_known_signmask_f32_known_positive_mag__nnan_exp10(float %
define float @copysign_known_signmask_f32_known_positive_mag_through_fence(float nofpclass(nan ninf nzero nsub nnorm) %sign.bit.known.zero, i32 %sign) {
; GFX9-LABEL: copysign_known_signmask_f32_known_positive_mag_through_fence:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 31, v1
; GFX9-NEXT: ;ARITH_FENCE
; GFX9-NEXT: s_brev_b32 s4, -2
; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 31, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
%signmask = shl i32 %sign, 31
%signmask.bitcast = bitcast i32 %signmask to float