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[GlobalIsel][X86] Add G_ADD/G_SUB i8/i16 and promotion legalization tests

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Add i8/i16/i24/i42 ADD/SUB test coverage
This commit is contained in:
Simon Pilgrim 2023-06-02 14:41:15 +01:00
parent db3d6aca14
commit ec24d36faa
2 changed files with 386 additions and 73 deletions
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210
llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir
View File

@ -3,12 +3,17 @@
# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s 2>%t -o - | FileCheck %s --check-prefix=X32
# RUN: FileCheck -check-prefix=ERR32 %s < %t
# ERR32: remark: <unknown>:0:0: unable to legalize instruction: %11:_(s32), %12:_(s1) = G_UADDO %7:_, %9:_ (in function: test_add_i42)
# ERR32: remark: <unknown>:0:0: unable to legalize instruction: %7:_(s32), %8:_(s1) = G_UADDO %3:_, %5:_ (in function: test_add_i64)
--- |
define void @test_add_i1() { ret void}
define void @test_add_i8() { ret void }
define void @test_add_i16() { ret void }
define void @test_add_i27() { ret void }
define void @test_add_i32() { ret void }
define void @test_add_i42() { ret void }
define void @test_add_i64() { ret void }
...
@ -18,6 +23,41 @@ name: test_add_i1
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_add_i1
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_add_i1
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_ADD %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_add_i8
# CHECK-LABEL: name: test_add_i1
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
@ -29,26 +69,83 @@ registers:
# CHECK: RET 0
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_add_i1
; X64-LABEL: name: test_add_i8
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
; X64: $eax = COPY [[ANYEXT]](s32)
; X64: RET 0
; X32-LABEL: name: test_add_i1
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC]]
; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_add_i8
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
; X32: $eax = COPY [[ANYEXT]](s32)
; X32: RET 0
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC]]
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_ADD %1, %1
%1(s8) = G_TRUNC %0(s32)
%2(s8) = G_ADD %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_add_i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_add_i16
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_add_i16
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s16) = G_TRUNC %0(s32)
%2(s16) = G_ADD %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_add_i27
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_add_i27
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; X64-NEXT: $eax = COPY [[ADD]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_add_i27
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; X32-NEXT: $eax = COPY [[ADD]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s27) = G_TRUNC %0(s32)
%2(s27) = G_ADD %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
@ -66,22 +163,58 @@ body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_add_i32
; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X64: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X64: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
; X64: $eax = COPY [[ADD]](s32)
; X64: RET 0
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
; X64-NEXT: $eax = COPY [[ADD]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_add_i32
; X32: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X32: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
; X32: $eax = COPY [[ADD]](s32)
; X32: RET 0
; X32-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
; X32-NEXT: $eax = COPY [[ADD]](s32)
; X32-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
%1(s32) = IMPLICIT_DEF
%2(s32) = G_ADD %0, %1
$eax = COPY %2
RET 0
...
---
name: test_add_i42
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_add_i42
; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY]]
; X64-NEXT: $rax = COPY [[ADD]](s64)
; X64-NEXT: RET 0
; X32-LABEL: name: test_add_i42
; X32: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s42) = G_TRUNC [[COPY]](s64)
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s42)
; X32-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s42)
; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT1]](s64)
; X32-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
; X32-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; X32-NEXT: [[TRUNC1:%[0-9]+]]:_(s42) = G_TRUNC [[MV]](s64)
; X32-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s42)
; X32-NEXT: $rax = COPY [[ANYEXT2]](s64)
; X32-NEXT: RET 0
%0(s64) = COPY $rdx
%1(s42) = G_TRUNC %0(s64)
%2(s42) = G_ADD %1, %1
%3:_(s64) = G_ANYEXT %2
$rax = COPY %3
RET 0
...
---
name: test_add_i64
@ -96,24 +229,23 @@ body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_add_i64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[DEF]], [[DEF1]]
; X64: $rax = COPY [[ADD]](s64)
; X64: RET 0
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[DEF]], [[DEF1]]
; X64-NEXT: $rax = COPY [[ADD]](s64)
; X64-NEXT: RET 0
; X32-LABEL: name: test_add_i64
; X32: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X32: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X32: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X32: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
; X32: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; X32: $rax = COPY [[MV]](s64)
; X32: RET 0
; X32-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X32-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
; X32-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; X32-NEXT: $rax = COPY [[MV]](s64)
; X32-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = IMPLICIT_DEF
%2(s64) = G_ADD %0, %1
$rax = COPY %2
RET 0
...

249
llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
View File

@ -1,18 +1,25 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=X64
# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s 2>%t -o - | FileCheck %s --check-prefix=X32
# RUN: FileCheck -check-prefix=ERR32 %s < %t
# ERR32: remark: <unknown>:0:0: unable to legalize instruction: %13:_(s32), %14:_(s1) = G_USUBE %8:_, %10:_, %12:_ (in function: test_sub_i42)
# ERR32: remark: <unknown>:0:0: unable to legalize instruction: %9:_(s32), %10:_(s1) = G_USUBE %4:_, %6:_, %8:_ (in function: test_sub_i64)
--- |
define void @test_sub_i1() { ret void}
define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
%ret = sub i32 %arg1, %arg2
ret i32 %ret
}
define void @test_sub_i8() { ret void }
define void @test_sub_i16() { ret void }
define void @test_sub_i27() { ret void }
define void @test_sub_i32() { ret void }
define void @test_sub_i42() { ret void }
define void @test_sub_i64() { ret void }
...
---
name: test_sub_i1
# CHECK-LABEL: name: test_sub_i1
alignment: 16
legalized: false
regBankSelected: false
@ -22,22 +29,125 @@ registers:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_sub_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[SUB]], [[C]]
; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; CHECK: RET 0
; X64-LABEL: name: test_sub_i1
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]]
; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s8)
; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_sub_i1
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]]
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s8)
; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_SUB %1, %1
%3:_(p0) = G_IMPLICIT_DEF
G_STORE %2, %3 :: (store (s1))
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_sub_i8
# CHECK-LABEL: name: test_sub_i1
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
# CHECK: %0(s32) = COPY $edx
# CHECK-NEXT: %3(s8) = G_TRUNC %0(s32)
# CHECK-NEXT: %4(s8) = G_TRUNC %0(s32)
# CHECK-NEXT: %5(s8) = G_SUB %3, %4
# CHECK: RET 0
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_sub_i8
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC]]
; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s8)
; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_sub_i8
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC]]
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s8)
; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s8) = G_TRUNC %0(s32)
%2(s8) = G_SUB %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_sub_i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_sub_i16
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; X64-NEXT: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[TRUNC]]
; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s16)
; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_sub_i16
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; X32-NEXT: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[TRUNC]]
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s16)
; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s16) = G_TRUNC %0(s32)
%2(s16) = G_SUB %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_sub_i27
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_sub_i27
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X64-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY]]
; X64-NEXT: $eax = COPY [[SUB]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_sub_i27
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; X32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY]]
; X32-NEXT: $eax = COPY [[SUB]](s32)
; X32-NEXT: RET 0
%0(s32) = COPY $edx
%1(s27) = G_TRUNC %0(s32)
%2(s27) = G_SUB %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
@ -45,26 +155,97 @@ name: test_sub_i32
alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; CHECK-LABEL: name: test_sub_i32
; CHECK: liveins: $edi, $esi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; CHECK: $eax = COPY [[SUB]](s32)
; CHECK: RET 0, implicit $eax
%0(s32) = COPY $edi
%1(s32) = COPY $esi
; X64-LABEL: name: test_sub_i32
; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X64-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[DEF]], [[DEF1]]
; X64-NEXT: $eax = COPY [[SUB]](s32)
; X64-NEXT: RET 0
; X32-LABEL: name: test_sub_i32
; X32: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X32-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; X32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[DEF]], [[DEF1]]
; X32-NEXT: $eax = COPY [[SUB]](s32)
; X32-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
%1(s32) = IMPLICIT_DEF
%2(s32) = G_SUB %0, %1
$eax = COPY %2(s32)
RET 0, implicit $eax
$eax = COPY %2
RET 0
...
---
name: test_sub_i42
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_sub_i42
; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY]]
; X64-NEXT: $rax = COPY [[SUB]](s64)
; X64-NEXT: RET 0
; X32-LABEL: name: test_sub_i42
; X32: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s42) = G_TRUNC [[COPY]](s64)
; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s42)
; X32-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s42)
; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT1]](s64)
; X32-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
; X32-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; X32-NEXT: [[TRUNC1:%[0-9]+]]:_(s42) = G_TRUNC [[MV]](s64)
; X32-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s42)
; X32-NEXT: $rax = COPY [[ANYEXT2]](s64)
; X32-NEXT: RET 0
%0(s64) = COPY $rdx
%1(s42) = G_TRUNC %0(s64)
%2(s42) = G_SUB %1, %1
%3:_(s64) = G_ANYEXT %2
$rax = COPY %3
RET 0
...
---
name: test_sub_i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_sub_i64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[DEF]], [[DEF1]]
; X64-NEXT: $rax = COPY [[SUB]](s64)
; X64-NEXT: RET 0
; X32-LABEL: name: test_sub_i64
; X32: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X32-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X32-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
; X32-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; X32-NEXT: $rax = COPY [[MV]](s64)
; X32-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = IMPLICIT_DEF
%2(s64) = G_SUB %0, %1
$rax = COPY %2
RET 0
...