[AArch64] Add SchedReadAdvance to the Neoverse-N3 scheduling model (#167302)
Introduce a description of late forwarding to the Neoverse-N3 scheduling model.
This commit is contained in:
Asher Dobrescu
GitHub
parent
f67409c3ec
commit
ec490b1062
@ -553,6 +553,107 @@ def N3Write_16c_16V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0,
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let NumMicroOps = 16;
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}
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//===----------------------------------------------------------------------===//
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// Define forwarded types
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// NOTE: SOG, p. 19, n. 2: Accumulator forwarding is not supported for
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// consumers of 64 bit multiply high operations?
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def N3Wr_FMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_FMA : SchedReadAdvance<2, [WriteFMul, N3Wr_FMA]>;
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def N3Wr_VMA : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_VMA : SchedReadAdvance<3, [N3Wr_VMA]>;
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def N3Wr_VMAL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_VMAL : SchedReadAdvance<3, [N3Wr_VMAL]>;
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def N3Wr_VMAH : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_VMAH : SchedReadAdvance<2, [N3Wr_VMAH]>;
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def N3Wr_VMASL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_VMASL : SchedReadAdvance<2, [N3Wr_VMASL]>;
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def N3Wr_ADA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }
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def N3Rd_ADA : SchedReadAdvance<3, [N3Wr_ADA]>;
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def N3Wr_VDOT : SchedWriteRes<[N3UnitV]> { let Latency = 3; }
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def N3Rd_VDOT : SchedReadAdvance<2, [N3Wr_VDOT]>;
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def N3Wr_VMMA : SchedWriteRes<[N3UnitV]> { let Latency = 3; }
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def N3Rd_VMMA : SchedReadAdvance<2, [N3Wr_VMMA]>;
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def N3Wr_FCMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_FCMA : SchedReadAdvance<2, [N3Wr_FCMA]>;
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def N3Wr_FPM : SchedWriteRes<[N3UnitV]> { let Latency = 3; }
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def N3Wr_FPMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_FPMA : SchedReadAdvance<2, [N3Wr_FPM, N3Wr_FPMA]>;
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def N3Wr_FPMAL : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_FPMAL : SchedReadAdvance<2, [N3Wr_FPMAL]>;
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def N3Wr_BFD : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_BFD : SchedReadAdvance<2, [N3Wr_BFD]>;
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def N3Wr_BFMMA : SchedWriteRes<[N3UnitV]> { let Latency = 5; }
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def N3Rd_BFMMA : SchedReadAdvance<2, [N3Wr_BFMMA]>;
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def N3Wr_BFMLA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_BFMLA : SchedReadAdvance<2, [N3Wr_BFMLA]>;
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def N3Wr_CRC : SchedWriteRes<[N3UnitM0]> { let Latency = 2; }
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def N3Rd_CRC : SchedReadAdvance<1, [N3Wr_CRC]>;
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def N3Wr_ZA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }
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def N3Rd_ZA : SchedReadAdvance<3, [N3Wr_ZA]>;
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def N3Wr_ZPA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }
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def N3Rd_ZPA : SchedReadAdvance<3, [N3Wr_ZPA]>;
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def N3Wr_ZSA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }
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def N3Rd_ZSA : SchedReadAdvance<3, [N3Wr_ZSA]>;
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def N3Wr_ZDOTB : SchedWriteRes<[N3UnitV]> { let Latency = 3; }
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def N3Rd_ZDOTB : SchedReadAdvance<2, [N3Wr_ZDOTB]>;
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def N3Wr_ZDOTH : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_ZDOTH : SchedReadAdvance<3, [N3Wr_ZDOTH]>;
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def N3Wr_ZCMABHS : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_ZCMABHS : SchedReadAdvance<3, [N3Wr_ZCMABHS]>;
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def N3Wr_ZCMAD : SchedWriteRes<[N3UnitV0, N3UnitV0]> { let Latency = 5; }
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def N3Rd_ZCMAD : SchedReadAdvance<2, [N3Wr_ZCMAD]>;
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def N3Wr_ZMMA : SchedWriteRes<[N3UnitV]> { let Latency = 3; }
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def N3Rd_ZMMA : SchedReadAdvance<2, [N3Wr_ZMMA]>;
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def N3Wr_ZMABHS : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_ZMABHS : SchedReadAdvance<3, [N3Wr_ZMABHS]>;
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def N3Wr_ZMAD : SchedWriteRes<[N3UnitV0, N3UnitV0]> { let Latency = 5; }
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def N3Rd_ZMAD : SchedReadAdvance<2, [N3Wr_ZMAD]>;
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def N3Wr_ZMAL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Rd_ZMAL : SchedReadAdvance<3, [N3Wr_ZMAL]>;
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def N3Wr_ZMASQL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Wr_ZMASQBHS : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }
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def N3Wr_ZMASQD : SchedWriteRes<[N3UnitV0, N3UnitV0]> { let Latency = 5; }
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def N3Rd_ZMASQ : SchedReadAdvance<2, [N3Wr_ZMASQL, N3Wr_ZMASQBHS,
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N3Wr_ZMASQD]>;
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def N3Wr_ZFCMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_ZFCMA : SchedReadAdvance<2, [N3Wr_ZFCMA]>;
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def N3Wr_ZFMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_ZFMA : SchedReadAdvance<2, [N3Wr_ZFMA]>;
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def N3Wr_ZFMAL : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_ZFMAL : SchedReadAdvance<2, [N3Wr_ZFMAL]>;
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def N3Wr_ZBFDOT : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_ZBFDOT : SchedReadAdvance<2, [N3Wr_ZBFDOT]>;
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def N3Wr_ZBFMMA : SchedWriteRes<[N3UnitV]> { let Latency = 5; }
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def N3Rd_ZBFMMA : SchedReadAdvance<2, [N3Wr_ZBFMMA]>;
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def N3Wr_ZBFMAL : SchedWriteRes<[N3UnitV]> { let Latency = 4; }
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def N3Rd_ZBFMAL : SchedReadAdvance<2, [N3Wr_ZBFMAL]>;
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// Miscellaneous
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// -----------------------------------------------------------------------------
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@ -832,10 +933,11 @@ def : SchedAlias<WriteFDiv , N3Write_7c_1V0>;
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def : InstRW<[N3Write_12c_1V0], (instrs FDIVDrr, FSQRTDr)>;
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// FP multiply
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def : SchedAlias<WriteFMul, N3Write_3c_1V>;
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def : WriteRes<WriteFMul, [N3UnitV]> { let Latency = 3; }
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// FP multiply accumulate
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def : InstRW<[N3Write_4c_1V], (instregex "^(FMADD|FMSUB|FNMADD|FNMSUB)[DHS]rrr$")>;
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def : InstRW<[N3Wr_FMA, ReadDefault, ReadDefault, N3Rd_FMA],
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(instregex "^(FMADD|FMSUB|FNMADD|FNMSUB)[DHS]rrr$")>;
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// FP round to integral
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def : InstRW<[N3Write_3c_1V0], (instregex "^FRINT([AIMNPXZ]|32X|64X|32Z|64Z)[DHS]r$")>;
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@ -969,7 +1071,7 @@ def : SchedAlias<WriteVq, N3Write_2c_1V>;
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// ASIMD absolute diff accum long
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// ASIMD pairwise add and accumulate long
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// ASIMD shift accumulate
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def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]ABAL?v",
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def : InstRW<[N3Wr_ADA, N3Rd_ADA], (instregex "^[SU]ABAL?v",
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"^[SU]ADALPv",
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"^[SU]R?SRAv")>;
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@ -984,10 +1086,11 @@ def : InstRW<[N3Write_6c_2V1], (instregex "^[SU]?ADDL?Vv16i8v$")>;
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// ASIMD dot product
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// ASIMD dot product using signed and unsigned integers
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def : InstRW<[N3Write_3c_1V], (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;
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def : InstRW<[N3Wr_VDOT, N3Rd_VDOT],
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(instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;
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// ASIMD matrix multiply-accumulate
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def : InstRW<[N3Write_3c_1V], (instrs SMMLA, UMMLA, USMMLA)>;
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def : InstRW<[N3Wr_VMMA, N3Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;
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// ASIMD max/min, reduce, 4H/4S
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def : InstRW<[N3Write_3c_1V1], (instregex "^[SU](MAX|MIN)Vv4i(16|32)v$")>;
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@ -1002,16 +1105,16 @@ def : InstRW<[N3Write_6c_2V1], (instregex "[SU](MAX|MIN)Vv16i8v$")>;
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def : InstRW<[N3Write_4c_1V0], (instregex "^MULv", "^SQ(R)?DMULHv")>;
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// ASIMD multiply accumulate
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def : InstRW<[N3Write_4c_1V0], (instregex "^MLAv", "^MLSv")>;
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def : InstRW<[N3Wr_VMA, N3Rd_VMA], (instregex "^MLAv", "^MLSv")>;
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// ASIMD multiply accumulate high
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def : InstRW<[N3Write_4c_1V0], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;
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def : InstRW<[N3Wr_VMAH, N3Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;
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// ASIMD multiply accumulate long
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def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;
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def : InstRW<[N3Wr_VMAL, N3Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;
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// ASIMD multiply accumulate saturating long
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def : InstRW<[N3Write_4c_1V0], (instregex "^SQDMLALv", "^SQDMLSLv")>;
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def : InstRW<[N3Wr_VMASL, N3Rd_VMASL], (instregex "^SQDMLALv", "^SQDMLSLv")>;
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// ASIMD multiply/multiply long (8x8) polynomial, D-form
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// ASIMD multiply/multiply long (8x8) polynomial, Q-form
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@ -1058,7 +1161,7 @@ def : InstRW<[N3Write_4c_1V1],
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def : InstRW<[N3Write_3c_1V], (instregex "^FCADDv")>;
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// ASIMD FP complex multiply add
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def : InstRW<[N3Write_4c_1V], (instregex "^FCMLAv")>;
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def : InstRW<[N3Wr_FCMA, N3Rd_FCMA], (instregex "^FCMLAv")>;
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// ASIMD FP convert, long (F16 to F32)
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def : InstRW<[N3Write_4c_2V0], (instregex "^FCVTL(v4|v8)i16")>;
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@ -1114,13 +1217,13 @@ def : InstRW<[N3Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
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def : InstRW<[N3Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
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// ASIMD FP multiply
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def : InstRW<[N3Write_3c_1V], (instregex "^FMULv", "^FMULXv")>;
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def : InstRW<[N3Wr_FPM], (instregex "^FMULv", "^FMULXv")>;
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// ASIMD FP multiply accumulate
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def : InstRW<[N3Write_4c_1V], (instregex "^FMLAv", "^FMLSv")>;
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def : InstRW<[N3Wr_FPMA, N3Rd_FPMA], (instregex "^FMLAv", "^FMLSv")>;
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// ASIMD FP multiply accumulate long
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def : InstRW<[N3Write_4c_1V], (instregex "^FMLALv", "^FMLSLv")>;
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def : InstRW<[N3Wr_FPMAL, N3Rd_FPMAL], (instregex "^FMLALv", "^FMLSLv")>;
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// ASIMD FP round, D-form F32 and Q-form F64
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def : InstRW<[N3Write_3c_1V0],
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@ -1157,13 +1260,14 @@ def : InstRW<[N3Write_13c_2V0], (instrs FSQRTv2f64)>;
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def : InstRW<[N3Write_4c_2V0], (instrs BFCVTN, BFCVTN2)>;
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// ASIMD dot product
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def : InstRW<[N3Write_4c_1V], (instrs BFDOTv4bf16, BFDOTv8bf16)>;
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def : InstRW<[N3Wr_BFD, N3Rd_BFD], (instrs BFDOTv4bf16, BFDOTv8bf16)>;
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// ASIMD matrix multiply accumulate
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def : InstRW<[N3Write_5c_1V], (instrs BFMMLA)>;
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def : InstRW<[N3Wr_BFMMA, N3Rd_BFMMA], (instrs BFMMLA)>;
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// ASIMD multiply accumulate long
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def : InstRW<[N3Write_4c_1V], (instrs BFMLALB, BFMLALBIdx, BFMLALT, BFMLALTIdx)>;
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def : InstRW<[N3Wr_BFMLA, N3Rd_BFMLA],
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(instrs BFMLALB, BFMLALBIdx, BFMLALT, BFMLALTIdx)>;
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// Scalar convert, F32 to BF16
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def : InstRW<[N3Write_3c_1V0], (instrs BFCVT)>;
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@ -1502,7 +1606,7 @@ def : InstRW<[N3Write_4c_1V0], (instrs SM4E, SM4ENCKEY)>;
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// -----------------------------------------------------------------------------
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// CRC checksum ops
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def : InstRW<[N3Write_2c_1M0], (instregex "^CRC32")>;
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def : InstRW<[N3Wr_CRC, N3Rd_CRC], (instregex "^CRC32")>;
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// SVE Predicate instructions
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// -----------------------------------------------------------------------------
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@ -1592,10 +1696,10 @@ def : InstRW<[N3Write_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",
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"^[SU]ABD_ZPZZ_[BHSD]")>;
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// Arithmetic, absolute diff accum
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def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;
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def : InstRW<[N3Wr_ZA, N3Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;
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// Arithmetic, absolute diff accum long
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def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>;
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def : InstRW<[N3Wr_ZA, N3Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>;
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// Arithmetic, absolute diff long
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def : InstRW<[N3Write_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>;
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@ -1629,7 +1733,8 @@ def : InstRW<[N3Write_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>;
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def : InstRW<[N3Write_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>;
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// Arithmetic, pairwise add and accum long
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def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]ADALP_ZPmZ_[HSD]$")>;
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def : InstRW<[N3Wr_ZPA, ReadDefault, N3Rd_ZPA],
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(instregex "^[SU]ADALP_ZPmZ_[HSD]$")>;
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// Arithmetic, shift
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def : InstRW<[N3Write_2c_1V1],
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@ -1642,7 +1747,7 @@ def : InstRW<[N3Write_2c_1V1],
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"^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;
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// Arithmetic, shift and accumulate
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def : InstRW<[N3Write_4c_1V1],
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def : InstRW<[N3Wr_ZSA, N3Rd_ZSA],
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(instregex "^(SRSRA|SSRA|URSRA|USRA)_ZZI_[BHSD]$")>;
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// Arithmetic, shift by immediate
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@ -1688,16 +1793,17 @@ def : InstRW<[N3Write_2c_1V],
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def : InstRW<[N3Write_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]$")>;
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// Complex dot product 8-bit element
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def : InstRW<[N3Write_3c_1V], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;
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def : InstRW<[N3Wr_ZDOTB, N3Rd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;
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// Complex dot product 16-bit element
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def : InstRW<[N3Write_4c_1V0], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;
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def : InstRW<[N3Wr_ZDOTH, N3Rd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;
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// Complex multiply-add B, H, S element size
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def : InstRW<[N3Write_4c_1V0], (instregex "^CMLA_ZZZ_[BHS]$", "^CMLA_ZZZI_[HS]$")>;
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def : InstRW<[N3Wr_ZCMABHS, N3Rd_ZCMABHS],
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(instregex "^CMLA_ZZZ_[BHS]$", "^CMLA_ZZZI_[HS]$")>;
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// Complex multiply-add D element size
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def : InstRW<[N3Write_5c_2V0], (instrs CMLA_ZZZ_D)>;
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def : InstRW<[N3Wr_ZCMAD, N3Rd_ZCMAD], (instrs CMLA_ZZZ_D)>;
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// Conditional extract operations, scalar form
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def : InstRW<[N3Write_8c_1M0_1V], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;
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@ -1736,13 +1842,14 @@ def : InstRW<[N3Write_16c_16V0], (instregex "^[SU]DIVR?_ZPmZ_D",
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"^[SU]DIV_ZPZZ_D")>;
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// Dot product, 8 bit
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def : InstRW<[N3Write_3c_1V], (instregex "^[SU]DOT_ZZZI?_BtoS$")>;
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def : InstRW<[N3Wr_ZDOTB, N3Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_BtoS$")>;
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// Dot product, 8 bit, using signed and unsigned integers
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def : InstRW<[N3Write_3c_1V], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;
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def : InstRW<[N3Wr_ZDOTB, N3Rd_ZDOTB],
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(instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;
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// Dot product, 16 bit
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def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]DOT_ZZZI?_HtoD$")>;
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def : InstRW<[N3Wr_ZDOTH, N3Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_HtoD$")>;
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// Duplicate, immediate and indexed form
|
||||
def : InstRW<[N3Write_2c_1V], (instregex "^DUP_ZI_[BHSD]$",
|
||||
@ -1804,7 +1911,7 @@ def : InstRW<[N3Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",
|
||||
def : InstRW<[N3Write_2c_1V], (instregex "^N?MATCH_PPzZZ_[BH]$")>;
|
||||
|
||||
// Matrix multiply-accumulate
|
||||
def : InstRW<[N3Write_3c_1V], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
|
||||
def : InstRW<[N3Wr_ZMMA, N3Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
|
||||
|
||||
// Move prefix
|
||||
def : InstRW<[N3Write_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",
|
||||
@ -1827,20 +1934,22 @@ def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$",
|
||||
"^[SU]MULL[BT]_ZZZ_[HSD]$")>;
|
||||
|
||||
// Multiply accumulate, B, H, S element size
|
||||
def : InstRW<[N3Write_4c_1V0], (instregex "^ML[AS]_ZZZI_[BHS]$",
|
||||
"^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;
|
||||
def : InstRW<[N3Wr_ZMABHS, ReadDefault, N3Rd_ZMABHS],
|
||||
(instregex "^ML[AS]_ZZZI_[BHS]$",
|
||||
"^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;
|
||||
|
||||
// Multiply accumulate, D element size
|
||||
def : InstRW<[N3Write_5c_2V0], (instregex "^ML[AS]_ZZZI_D$",
|
||||
def : InstRW<[N3Wr_ZMAD, ReadDefault, N3Rd_ZMAD], (instregex "^ML[AS]_ZZZI_D$",
|
||||
"^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;
|
||||
|
||||
// Multiply accumulate long
|
||||
def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$",
|
||||
def : InstRW<[N3Wr_ZMAL, N3Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$",
|
||||
"^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>;
|
||||
|
||||
// Multiply accumulate saturating doubling long regular
|
||||
def : InstRW<[N3Write_4c_1V0], (instregex "^SQDML[AS](LB|LT|LBT)_ZZZ_[HSD]$",
|
||||
"^SQDML[AS](LB|LT)_ZZZI_[SD]$")>;
|
||||
def : InstRW<[N3Wr_ZMASQL, N3Rd_ZMASQ],
|
||||
(instregex "^SQDML[AS](LB|LT|LBT)_ZZZ_[HSD]$",
|
||||
"^SQDML[AS](LB|LT)_ZZZI_[SD]$")>;
|
||||
|
||||
// Multiply saturating doubling high, B, H, S element size
|
||||
def : InstRW<[N3Write_4c_1V0], (instregex "^SQDMULH_ZZZ_[BHS]$",
|
||||
@ -1854,13 +1963,13 @@ def : InstRW<[N3Write_4c_1V0], (instregex "^SQDMULL[BT]_ZZZ_[HSD]$",
|
||||
"^SQDMULL[BT]_ZZZI_[SD]$")>;
|
||||
|
||||
// Multiply saturating rounding doubling regular/complex accumulate, B, H, S element size
|
||||
def : InstRW<[N3Write_4c_1V0], (instregex "^SQRDML[AS]H_ZZZ_[BHS]$",
|
||||
def : InstRW<[N3Wr_ZMASQBHS, N3Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZ_[BHS]$",
|
||||
"^SQRDCMLAH_ZZZ_[BHS]$",
|
||||
"^SQRDML[AS]H_ZZZI_[HS]$",
|
||||
"^SQRDCMLAH_ZZZI_[HS]$")>;
|
||||
|
||||
// Multiply saturating rounding doubling regular/complex accumulate, D element size
|
||||
def : InstRW<[N3Write_5c_2V0], (instregex "^SQRDML[AS]H_ZZZI?_D$",
|
||||
def : InstRW<[N3Wr_ZMASQD, N3Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D$",
|
||||
"^SQRDCMLAH_ZZZ_D$")>;
|
||||
|
||||
// Multiply saturating rounding doubling regular/complex, B, H, S element size
|
||||
@ -1948,8 +2057,9 @@ def : InstRW<[N3Write_2c_1V], (instregex "^FAC(GE|GT)_PPzZZ_[HSD]$",
|
||||
def : InstRW<[N3Write_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]$")>;
|
||||
|
||||
// Floating point complex multiply add
|
||||
def : InstRW<[N3Write_4c_1V], (instregex "^FCMLA_ZPmZZ_[HSD]$",
|
||||
"^FCMLA_ZZZI_[HS]$")>;
|
||||
def : InstRW<[N3Wr_ZFCMA, ReadDefault, N3Rd_ZFCMA],
|
||||
(instregex "^FCMLA_ZPmZZ_[HSD]")>;
|
||||
def : InstRW<[N3Wr_ZFCMA, N3Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;
|
||||
|
||||
// Floating point convert, long or narrow (F16 to F32 or F32 to F16)
|
||||
def : InstRW<[N3Write_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",
|
||||
@ -2014,12 +2124,15 @@ def : InstRW<[N3Write_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",
|
||||
"^FMUL_ZPZ[IZ]_[HSD]")>;
|
||||
|
||||
// Floating point multiply accumulate
|
||||
def : InstRW<[N3Write_4c_1V], (instregex "^F(N?M(AD|SB)|N?ML[AS])_ZPmZZ_[HSD]$",
|
||||
"^FN?ML[AS]_ZPZZZ_[HSD]",
|
||||
"^FML[AS]_ZZZI_[HSD]$")>;
|
||||
def : InstRW<[N3Wr_ZFMA, ReadDefault, N3Rd_ZFMA],
|
||||
(instregex "^FN?ML[AS]_ZPmZZ_[HSD]",
|
||||
"^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;
|
||||
def : InstRW<[N3Wr_ZFMA, N3Rd_ZFMA],
|
||||
(instregex "^FML[AS]_ZZZI_[HSD]",
|
||||
"^FN?ML[AS]_ZPZZZ_[HSD]")>;
|
||||
|
||||
// Floating point multiply add/sub accumulate long
|
||||
def : InstRW<[N3Write_4c_1V], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;
|
||||
def : InstRW<[N3Wr_ZFMAL, N3Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;
|
||||
|
||||
// Floating point reciprocal estimate, F16
|
||||
def : InstRW<[N3Write_6c_4V0], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;
|
||||
@ -2079,13 +2192,13 @@ def : InstRW<[N3Write_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]$")>;
|
||||
def : InstRW<[N3Write_4c_2V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;
|
||||
|
||||
// Dot product
|
||||
def : InstRW<[N3Write_4c_1V], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;
|
||||
def : InstRW<[N3Wr_ZBFDOT, N3Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;
|
||||
|
||||
// Matrix multiply accumulate
|
||||
def : InstRW<[N3Write_5c_1V], (instrs BFMMLA_ZZZ_HtoS)>;
|
||||
def : InstRW<[N3Wr_ZBFMMA, N3Rd_ZBFMMA], (instrs BFMMLA_ZZZ_HtoS)>;
|
||||
|
||||
// Multiply accumulate long
|
||||
def : InstRW<[N3Write_4c_1V], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>;
|
||||
def : InstRW<[N3Wr_ZBFMAL, N3Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>;
|
||||
|
||||
// SVE Load instructions
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
2034
llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-forwarding.s
Normal file
2034
llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-forwarding.s
Normal file
File diff suppressed because it is too large
Load Diff
@ -3685,21 +3685,21 @@ zip2 z31.s, z31.s, z31.s
|
||||
# CHECK-NEXT: 1 2 0.50 clz z31.h, p7/m, z31.h
|
||||
# CHECK-NEXT: 1 2 0.50 clz z31.s, p7/m, z31.s
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z0.b, z1.b, z2.b, #0
|
||||
# CHECK-NEXT: 2 5 2.00 cmla z0.d, z1.d, z2.d, #0
|
||||
# CHECK-NEXT: 1 5 2.00 cmla z0.d, z1.d, z2.d, #0
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z0.h, z1.h, z2.h, #0
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z0.h, z1.h, z2.h[0], #0
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z0.s, z1.s, z2.s, #0
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z0.s, z1.s, z2.s[0], #0
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z15.b, z16.b, z17.b, #270
|
||||
# CHECK-NEXT: 2 5 2.00 cmla z15.d, z16.d, z17.d, #270
|
||||
# CHECK-NEXT: 1 5 2.00 cmla z15.d, z16.d, z17.d, #270
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z15.h, z16.h, z17.h, #270
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z15.s, z16.s, z17.s, #270
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z29.b, z30.b, z31.b, #90
|
||||
# CHECK-NEXT: 2 5 2.00 cmla z29.d, z30.d, z31.d, #90
|
||||
# CHECK-NEXT: 1 5 2.00 cmla z29.d, z30.d, z31.d, #90
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z29.h, z30.h, z31.h, #90
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z29.s, z30.s, z31.s, #90
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z31.b, z31.b, z31.b, #180
|
||||
# CHECK-NEXT: 2 5 2.00 cmla z31.d, z31.d, z31.d, #180
|
||||
# CHECK-NEXT: 1 5 2.00 cmla z31.d, z31.d, z31.d, #180
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z31.h, z30.h, z7.h[0], #180
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z31.h, z31.h, z31.h, #180
|
||||
# CHECK-NEXT: 1 4 1.00 cmla z31.s, z30.s, z7.s[0], #180
|
||||
@ -4938,7 +4938,7 @@ zip2 z31.s, z31.s, z31.s
|
||||
# CHECK-NEXT: 1 2 1.00 lsrr z0.h, p0/m, z0.h, z0.h
|
||||
# CHECK-NEXT: 1 2 1.00 lsrr z0.s, p0/m, z0.s, z0.s
|
||||
# CHECK-NEXT: 1 4 1.00 mad z0.b, p7/m, z1.b, z31.b
|
||||
# CHECK-NEXT: 2 5 2.00 mad z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 5 2.00 mad z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 4 1.00 mad z0.h, p7/m, z1.h, z31.h
|
||||
# CHECK-NEXT: 1 4 1.00 mad z0.s, p7/m, z1.s, z31.s
|
||||
# CHECK-NEXT: 1 2 0.50 match p0.b, p0/z, z0.b, z0.b
|
||||
@ -4946,15 +4946,15 @@ zip2 z31.s, z31.s, z31.s
|
||||
# CHECK-NEXT: 1 2 0.50 match p15.b, p7/z, z30.b, z31.b
|
||||
# CHECK-NEXT: 1 2 0.50 match p15.h, p7/z, z30.h, z31.h
|
||||
# CHECK-NEXT: 1 4 1.00 mla z0.b, p7/m, z1.b, z31.b
|
||||
# CHECK-NEXT: 2 5 2.00 mla z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 2 5 2.00 mla z0.d, z1.d, z7.d[1]
|
||||
# CHECK-NEXT: 1 5 2.00 mla z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 5 2.00 mla z0.d, z1.d, z7.d[1]
|
||||
# CHECK-NEXT: 1 4 1.00 mla z0.h, p7/m, z1.h, z31.h
|
||||
# CHECK-NEXT: 1 4 1.00 mla z0.h, z1.h, z7.h[7]
|
||||
# CHECK-NEXT: 1 4 1.00 mla z0.s, p7/m, z1.s, z31.s
|
||||
# CHECK-NEXT: 1 4 1.00 mla z0.s, z1.s, z7.s[3]
|
||||
# CHECK-NEXT: 1 4 1.00 mls z0.b, p7/m, z1.b, z31.b
|
||||
# CHECK-NEXT: 2 5 2.00 mls z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 2 5 2.00 mls z0.d, z1.d, z7.d[1]
|
||||
# CHECK-NEXT: 1 5 2.00 mls z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 5 2.00 mls z0.d, z1.d, z7.d[1]
|
||||
# CHECK-NEXT: 1 4 1.00 mls z0.h, p7/m, z1.h, z31.h
|
||||
# CHECK-NEXT: 1 4 1.00 mls z0.h, z1.h, z7.h[7]
|
||||
# CHECK-NEXT: 1 4 1.00 mls z0.s, p7/m, z1.s, z31.s
|
||||
@ -5072,7 +5072,7 @@ zip2 z31.s, z31.s, z31.s
|
||||
# CHECK-NEXT: 1 1 0.25 U mrs x3, ZCR_EL2
|
||||
# CHECK-NEXT: 1 1 0.25 U mrs x3, ZCR_EL3
|
||||
# CHECK-NEXT: 1 4 1.00 msb z0.b, p7/m, z1.b, z31.b
|
||||
# CHECK-NEXT: 2 5 2.00 msb z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 5 2.00 msb z0.d, p7/m, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 4 1.00 msb z0.h, p7/m, z1.h, z31.h
|
||||
# CHECK-NEXT: 1 4 1.00 msb z0.s, p7/m, z1.s, z31.s
|
||||
# CHECK-NEXT: 1 1 0.25 U msr ZCR_EL1, x3
|
||||
@ -5790,35 +5790,35 @@ zip2 z31.s, z31.s, z31.s
|
||||
# CHECK-NEXT: 1 2 0.50 sqneg z31.h, p7/m, z31.h
|
||||
# CHECK-NEXT: 1 2 0.50 sqneg z31.s, p7/m, z31.s
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z0.b, z1.b, z2.b, #0
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdcmlah z0.d, z1.d, z2.d, #0
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdcmlah z0.d, z1.d, z2.d, #0
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z0.h, z1.h, z2.h, #0
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z0.h, z1.h, z2.h[0], #0
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z0.s, z1.s, z2.s, #0
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z0.s, z1.s, z2.s[0], #0
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z15.b, z16.b, z17.b, #270
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdcmlah z15.d, z16.d, z17.d, #270
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdcmlah z15.d, z16.d, z17.d, #270
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z15.h, z16.h, z17.h, #270
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z15.s, z16.s, z17.s, #270
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z29.b, z30.b, z31.b, #90
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdcmlah z29.d, z30.d, z31.d, #90
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdcmlah z29.d, z30.d, z31.d, #90
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z29.h, z30.h, z31.h, #90
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z29.s, z30.s, z31.s, #90
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z31.b, z31.b, z31.b, #180
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdcmlah z31.d, z31.d, z31.d, #180
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdcmlah z31.d, z31.d, z31.d, #180
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z31.h, z30.h, z7.h[0], #180
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z31.h, z31.h, z31.h, #180
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z31.s, z30.s, z7.s[0], #180
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdcmlah z31.s, z31.s, z31.s, #180
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlah z0.b, z1.b, z31.b
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdmlah z0.d, z1.d, z15.d[1]
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdmlah z0.d, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdmlah z0.d, z1.d, z15.d[1]
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdmlah z0.d, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlah z0.h, z1.h, z31.h
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlah z0.h, z1.h, z7.h[7]
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlah z0.s, z1.s, z31.s
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlah z0.s, z1.s, z7.s[3]
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlsh z0.b, z1.b, z31.b
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdmlsh z0.d, z1.d, z15.d[1]
|
||||
# CHECK-NEXT: 2 5 2.00 sqrdmlsh z0.d, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdmlsh z0.d, z1.d, z15.d[1]
|
||||
# CHECK-NEXT: 1 5 2.00 sqrdmlsh z0.d, z1.d, z31.d
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlsh z0.h, z1.h, z31.h
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlsh z0.h, z1.h, z7.h[7]
|
||||
# CHECK-NEXT: 1 4 1.00 sqrdmlsh z0.s, z1.s, z31.s
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user