From ec4dd862bf548c157b2c992efe4f10da4f04c4e2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 6 Jan 2022 08:24:32 -0800 Subject: [PATCH] [RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics. The 0 immediate can't be selected to vmsgtu.vi/vmsleu.vi by decrementing the immediate. To prevent his we had special patterns that provided alternate lowering for the 0 cases. This relied on tablegen prioritizing the 0 pattern over the sim5_plus1 range. This patch introduces simm5_plus1_nonzero that excludes 0. It also excludes the special case for vmsltu.vi since we can just use vmsltu.vx and let the 0 be selected to X0. This is an alternative to some of the changes in D116584. Reviewed By: Chenbing.Zheng, asb Differential Revision: https://reviews.llvm.org/D116723 --- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 3 +++ .../Target/RISCV/RISCVInstrInfoVPseudos.td | 22 +++++++++---------- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll | 4 ++-- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll | 4 ++-- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 173ae43a08d6..8e2bb27c6a98 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -77,6 +77,9 @@ def simm5_plus1 : Operand, ImmLeaf(Imm) && Imm != -16) || Imm == 16);}]>; + //===----------------------------------------------------------------------===// // Scheduling definitions. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 7970ad0dad60..3b6d19ae0981 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3700,23 +3700,24 @@ multiclass VPatConversionVF_WF { } } -multiclass VPatCompare_VI { +multiclass VPatCompare_VI { foreach vti = AllIntegerVectors in { defvar Intr = !cast(intrinsic); defvar Pseudo = !cast(inst#"_VI_"#vti.LMul.MX); def : Pat<(vti.Mask (Intr (vti.Vector vti.RegClass:$rs1), - (vti.Scalar simm5_plus1:$rs2), + (vti.Scalar ImmType:$rs2), VLOpFrag)), - (Pseudo vti.RegClass:$rs1, (DecImm simm5_plus1:$rs2), + (Pseudo vti.RegClass:$rs1, (DecImm ImmType:$rs2), GPR:$vl, vti.Log2SEW)>; defvar IntrMask = !cast(intrinsic # "_mask"); defvar PseudoMask = !cast(inst#"_VI_"#vti.LMul.MX#"_MASK"); def : Pat<(vti.Mask (IntrMask (vti.Mask VR:$merge), (vti.Vector vti.RegClass:$rs1), - (vti.Scalar simm5_plus1:$rs2), + (vti.Scalar ImmType:$rs2), (vti.Mask V0), VLOpFrag)), - (PseudoMask VR:$merge, vti.RegClass:$rs1, (DecImm simm5_plus1:$rs2), + (PseudoMask VR:$merge, vti.RegClass:$rs1, (DecImm ImmType:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; } } @@ -4521,15 +4522,12 @@ defm : VPatBinarySwappedM_VV<"int_riscv_vmsge", "PseudoVMSLE", AllIntegerVectors // avoids the user needing to know that there is no vmslt(u).vi instruction. // Similar for vmsge(u).vx intrinsics using vmslt(u).vi. defm : VPatCompare_VI<"int_riscv_vmslt", "PseudoVMSLE">; -defm : VPatCompare_VI<"int_riscv_vmsltu", "PseudoVMSLEU">; -// Special cases to avoid matching vmsltu.vi 0 (always false) to -// vmsleu.vi -1 (always true). Instead match to vmsne.vv. -defm : VPatCompareUnsignedZero<"int_riscv_vmsltu", "PseudoVMSNE">; +defm : VPatCompare_VI<"int_riscv_vmsltu", "PseudoVMSLEU", simm5_plus1_nonzero>; defm : VPatCompare_VI<"int_riscv_vmsge", "PseudoVMSGT">; -defm : VPatCompare_VI<"int_riscv_vmsgeu", "PseudoVMSGTU">; -// Special cases to avoid matching vmsgeu.vi 0 (always true) to -// vmsgtu.vi -1 (always false). Instead match to vmsne.vv. +defm : VPatCompare_VI<"int_riscv_vmsgeu", "PseudoVMSGTU", simm5_plus1_nonzero>; +// Special cases for vmsgeu.vi 0 (always true). Instead match to vmsne.vv. +// FIXME: We could match this to vmset.m or vmset.m+vmand.mm. defm : VPatCompareUnsignedZero<"int_riscv_vmsgeu", "PseudoVMSEQ">; //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll index 830702db9ec1..9652a76bdb82 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll @@ -2085,7 +2085,7 @@ define @intrinsic_vmsltu_mask_vi_nxv2i16_i16( ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vv v10, v8, v8, v0.t +; CHECK-NEXT: vmsltu.vx v10, v8, zero, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: @@ -2103,7 +2103,7 @@ define @intrinsic_vmsltu_vi_nxv4i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsne.vv v0, v8, v8 +; CHECK-NEXT: vmsltu.vx v0, v8, zero ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.nxv4i16.i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll index 7f39a270b162..82491fd181e1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll @@ -2049,7 +2049,7 @@ define @intrinsic_vmsltu_mask_vi_nxv2i16_i16( ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vv v10, v8, v8, v0.t +; CHECK-NEXT: vmsltu.vx v10, v8, zero, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: @@ -2067,7 +2067,7 @@ define @intrinsic_vmsltu_vi_nxv4i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsne.vv v0, v8, v8 +; CHECK-NEXT: vmsltu.vx v0, v8, zero ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.nxv4i16.i16(