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AMDGPU: Avoid report_fatal_error on ds ordered intrinsics (#145202)

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Matt Arsenault 2025-06-23 13:09:09 +09:00 committed by GitHub
parent c7165587e4
commit ed155ff9f2
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GPG Key ID: B5690EEEBB952194
3 changed files with 62 additions and 12 deletions
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21
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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@ -1767,8 +1767,12 @@ bool AMDGPUInstructionSelector::selectDSOrderedIntrinsic(
bool WaveRelease = MI.getOperand(8).getImm() != 0;
bool WaveDone = MI.getOperand(9).getImm() != 0;
if (WaveDone && !WaveRelease)
report_fatal_error("ds_ordered_count: wave_done requires wave_release");
if (WaveDone && !WaveRelease) {
// TODO: Move this to IR verifier
const Function &Fn = MF->getFunction();
Fn.getContext().diagnose(DiagnosticInfoUnsupported(
Fn, "ds_ordered_count: wave_done requires wave_release", DL));
}
unsigned OrderedCountIndex = IndexOperand & 0x3f;
IndexOperand &= ~0x3f;
@ -1779,13 +1783,18 @@ bool AMDGPUInstructionSelector::selectDSOrderedIntrinsic(
IndexOperand &= ~(0xf << 24);
if (CountDw < 1 || CountDw > 4) {
report_fatal_error(
"ds_ordered_count: dword count must be between 1 and 4");
const Function &Fn = MF->getFunction();
Fn.getContext().diagnose(DiagnosticInfoUnsupported(
Fn, "ds_ordered_count: dword count must be between 1 and 4", DL));
CountDw = 1;
}
}
if (IndexOperand)
report_fatal_error("ds_ordered_count: bad index operand");
if (IndexOperand) {
const Function &Fn = MF->getFunction();
Fn.getContext().diagnose(DiagnosticInfoUnsupported(
Fn, "ds_ordered_count: bad index operand", DL));
}
unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1;
unsigned ShaderType = SIInstrInfo::getDSShaderTypeValue(*MF);

23
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -9330,16 +9330,27 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
IndexOperand &= ~(0xf << 24);
if (CountDw < 1 || CountDw > 4) {
report_fatal_error(
"ds_ordered_count: dword count must be between 1 and 4");
const Function &Fn = DAG.getMachineFunction().getFunction();
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
Fn, "ds_ordered_count: dword count must be between 1 and 4",
DL.getDebugLoc()));
CountDw = 1;
}
}
if (IndexOperand)
report_fatal_error("ds_ordered_count: bad index operand");
if (IndexOperand) {
const Function &Fn = DAG.getMachineFunction().getFunction();
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
Fn, "ds_ordered_count: bad index operand", DL.getDebugLoc()));
}
if (WaveDone && !WaveRelease)
report_fatal_error("ds_ordered_count: wave_done requires wave_release");
if (WaveDone && !WaveRelease) {
// TODO: Move this to IR verifier
const Function &Fn = DAG.getMachineFunction().getFunction();
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
Fn, "ds_ordered_count: wave_done requires wave_release",
DL.getDebugLoc()));
}
unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1;
unsigned ShaderType =

30
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll Normal file
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@ -0,0 +1,30 @@
; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 -filetype=null %s 2>&1 | FileCheck %s
; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 -filetype=null %s 2>&1 | FileCheck %s
; CHECK: error: <unknown>:0:0: in function ds_ordered_add_dword_count_too_low void (ptr addrspace(2), ptr addrspace(1)): ds_ordered_count: dword count must be between 1 and 4
define amdgpu_kernel void @ds_ordered_add_dword_count_too_low(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
%val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 0, i1 true, i1 true)
store i32 %val, ptr addrspace(1) %out
ret void
}
; CHECK: error: <unknown>:0:0: in function ds_ordered_add_dword_count_too_high void (ptr addrspace(2), ptr addrspace(1)): ds_ordered_count: dword count must be between 1 and 4
define amdgpu_kernel void @ds_ordered_add_dword_count_too_high(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
%val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 5, i1 true, i1 true)
store i32 %val, ptr addrspace(1) %out
ret void
}
; CHECK: error: <unknown>:0:0: in function ds_ordered_add_bad_index_operand void (ptr addrspace(2), ptr addrspace(1)): ds_ordered_count: bad index operand
define amdgpu_kernel void @ds_ordered_add_bad_index_operand(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
%val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 1, i1 false, i32 -1, i1 true, i1 true)
store i32 %val, ptr addrspace(1) %out
ret void
}
; CHECK: error: <unknown>:0:0: in function ds_ordered_add_dword_count_wave_done_without_wave_release void (ptr addrspace(2), ptr addrspace(1)): ds_ordered_count: wave_done requires wave_release
define amdgpu_kernel void @ds_ordered_add_dword_count_wave_done_without_wave_release(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
%val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 false, i1 true)
store i32 %val, ptr addrspace(1) %out
ret void
}