diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index a32f6a566493..566cf632f774 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3174,7 +3174,7 @@ multiclass VPseudoTernaryWithPolicyRoundingMode TargetConstraintType = 1> { - let VLMul = MInfo.value in { + let VLMul = MInfo.value, SEW = sew in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); let isCommutable = Commutable in def suffix : diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s index 64e3ed98c03d..ae6076178aa8 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s @@ -2333,22 +2333,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: 1 228 228.00 228 VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 # CHECK-NEXT: 1 228 228.00 228 VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 # CHECK-NEXT: 1 228 228.00 228 VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 23 16.00 23 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: 1 228 228.00 228 VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 # CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 # CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v v8, v24 @@ -2394,22 +2394,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: 1 456 456.00 456 VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 # CHECK-NEXT: 1 456 456.00 456 VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 # CHECK-NEXT: 1 456 456.00 456 VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 39 32.00 39 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: 1 456 456.00 456 VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 # CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 # CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v v8, v24 @@ -2455,22 +2455,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: 1 912 912.00 912 VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 # CHECK-NEXT: 1 912 912.00 912 VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 # CHECK-NEXT: 1 912 912.00 912 VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 71 64.00 71 VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: 1 912 912.00 912 VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 # CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 # CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v v8, v24 @@ -2516,22 +2516,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: 1 1824 1824.00 1824 VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 # CHECK-NEXT: 1 1824 1824.00 1824 VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 # CHECK-NEXT: 1 1824 1824.00 1824 VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 135 128.00 135 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: 1 1824 1824.00 1824 VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 # CHECK-NEXT: 1 8 16.00 8 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 # CHECK-NEXT: 1 8 16.00 8 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v v8, v24 @@ -3255,7 +3255,7 @@ vfncvt.rod.f.f.w v8, v16 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] -# CHECK-NEXT: - - 32.00 - 58006.00 2446.00 1558.00 - - +# CHECK-NEXT: - - 32.00 - 61638.00 2174.00 1558.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions: @@ -3941,22 +3941,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: - - - - 229.00 - 1.00 - - vfdiv.vv v8, v16, v24 # CHECK-NEXT: - - - - 229.00 - 1.00 - - vfdiv.vf v8, v16, fs0 # CHECK-NEXT: - - - - 229.00 - 1.00 - - vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 1.50 1.50 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 - 1.00 - - vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: - - - - 229.00 - 1.00 - - vfsqrt.v v8, v24 # CHECK-NEXT: - - - - 3.00 - 1.00 - - vfrsqrt7.v v8, v24 # CHECK-NEXT: - - - - 3.00 - 1.00 - - vfrec7.v v8, v24 @@ -4002,22 +4002,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: - - - - 457.00 - 1.00 - - vfdiv.vv v8, v16, v24 # CHECK-NEXT: - - - - 457.00 - 1.00 - - vfdiv.vf v8, v16, fs0 # CHECK-NEXT: - - - - 457.00 - 1.00 - - vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 2.50 2.50 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 33.00 - 1.00 - - vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: - - - - 457.00 - 1.00 - - vfsqrt.v v8, v24 # CHECK-NEXT: - - - - 5.00 - 1.00 - - vfrsqrt7.v v8, v24 # CHECK-NEXT: - - - - 5.00 - 1.00 - - vfrec7.v v8, v24 @@ -4063,22 +4063,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: - - - - 913.00 - 1.00 - - vfdiv.vv v8, v16, v24 # CHECK-NEXT: - - - - 913.00 - 1.00 - - vfdiv.vf v8, v16, fs0 # CHECK-NEXT: - - - - 913.00 - 1.00 - - vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 4.50 4.50 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 65.00 - 1.00 - - vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: - - - - 913.00 - 1.00 - - vfsqrt.v v8, v24 # CHECK-NEXT: - - - - 9.00 - 1.00 - - vfrsqrt7.v v8, v24 # CHECK-NEXT: - - - - 9.00 - 1.00 - - vfrec7.v v8, v24 @@ -4124,22 +4124,22 @@ vfncvt.rod.f.f.w v8, v16 # CHECK-NEXT: - - - - 1825.00 - 1.00 - - vfdiv.vv v8, v16, v24 # CHECK-NEXT: - - - - 1825.00 - 1.00 - - vfdiv.vf v8, v16, fs0 # CHECK-NEXT: - - - - 1825.00 - 1.00 - - vfrdiv.vf v8, v16, fs0 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmacc.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmacc.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmsac.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmsac.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmadd.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmadd.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfmsub.vf v8, fs0, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmsub.vv v8, v16, v24 -# CHECK-NEXT: - - - - 8.50 8.50 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 129.00 - 1.00 - - vfnmsub.vf v8, fs0, v24 # CHECK-NEXT: - - - - 1825.00 - 1.00 - - vfsqrt.v v8, v24 # CHECK-NEXT: - - - - 17.00 - 1.00 - - vfrsqrt7.v v8, v24 # CHECK-NEXT: - - - - 17.00 - 1.00 - - vfrec7.v v8, v24 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test index 282d278002c2..af4fb0f308ee 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test @@ -596,13 +596,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMACC_VF vfwmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMACC_VF vfwmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMACC_VV vfwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -614,13 +614,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMACC_VV vfwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMACC_VV vfwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMACC_VV vfwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMACC_VV vfwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMACC_VV vfwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VF vfwmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -632,13 +632,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VF vfwmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMSAC_VF vfwmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VV vfwmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -650,13 +650,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMSAC_VV vfwmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -668,13 +668,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VV vfwnmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -686,13 +686,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMACC_VV vfwnmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -704,13 +704,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -722,13 +722,13 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 # CHECK: Resources: # CHECK-NEXT: [0] - SMX60_FP diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test index 9fbb1f49e664..474ee41e1060 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test @@ -736,11 +736,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSAC_VV vfmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMSAC_VV vfmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMSAC_VV vfmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMSAC_VV vfmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMSAC_VV vfmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMSAC_VV vfmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMSAC_VV vfmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSAC_VV vfmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -766,11 +766,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSAC_VF vfmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMSAC_VF vfmsac.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMSAC_VF vfmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMSAC_VF vfmsac.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMSAC_VF vfmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMSAC_VF vfmsac.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMSAC_VF vfmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSAC_VF vfmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -796,11 +796,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSUB_VV vfmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMSUB_VV vfmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMSUB_VV vfmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMSUB_VV vfmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMSUB_VV vfmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMSUB_VV vfmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMSUB_VV vfmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSUB_VV vfmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -826,11 +826,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSUB_VF vfmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMSUB_VF vfmsub.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMSUB_VF vfmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMSUB_VF vfmsub.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMSUB_VF vfmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMSUB_VF vfmsub.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMSUB_VF vfmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMSUB_VF vfmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -916,11 +916,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMACC_VF vfmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMACC_VF vfmacc.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMACC_VF vfmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMACC_VF vfmacc.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMACC_VF vfmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMACC_VF vfmacc.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMACC_VF vfmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMACC_VF vfmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -946,11 +946,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMACC_VV vfmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMACC_VV vfmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMACC_VV vfmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMACC_VV vfmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMACC_VV vfmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMACC_VV vfmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMACC_VV vfmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMACC_VV vfmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -976,11 +976,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMADD_VF vfmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMADD_VF vfmadd.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMADD_VF vfmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMADD_VF vfmadd.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMADD_VF vfmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMADD_VF vfmadd.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMADD_VF vfmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMADD_VF vfmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1006,11 +1006,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMADD_VV vfmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFMADD_VV vfmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFMADD_VV vfmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFMADD_VV vfmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFMADD_VV vfmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFMADD_VV vfmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFMADD_VV vfmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMADD_VV vfmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1126,11 +1126,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMACC_VF vfnmacc.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMACC_VF vfnmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1156,11 +1156,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMACC_VV vfnmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMACC_VV vfnmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMACC_VV vfnmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMACC_VV vfnmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMACC_VV vfnmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMACC_VV vfnmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMACC_VV vfnmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMACC_VV vfnmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1186,11 +1186,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMADD_VF vfnmadd.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMADD_VF vfnmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1216,11 +1216,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMADD_VV vfnmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMADD_VV vfnmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMADD_VV vfnmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMADD_VV vfnmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMADD_VV vfnmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMADD_VV vfnmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMADD_VV vfnmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMADD_VV vfnmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1246,11 +1246,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMSAC_VF vfnmsac.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMSAC_VF vfnmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1276,11 +1276,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMSAC_VV vfnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMSAC_VV vfnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1306,11 +1306,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMSUB_VF vfnmsub.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMSUB_VF vfnmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu @@ -1336,11 +1336,11 @@ # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFNMSUB_VV vfnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFNMSUB_VV vfnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 7 4.00 7 SMX60_VFP[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu