From eda72ddeaea69a0fc7107f79d22afc1d426fd30b Mon Sep 17 00:00:00 2001 From: vangthao95 Date: Fri, 13 Mar 2026 11:33:59 -0700 Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for s_setprio/sethalt/nop (#186244) --- llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 3 +++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll | 4 ++-- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index 58ffa69cece4..ef27b04bb42e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -1463,6 +1463,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, // readfirstlaning just in case register is not in sgpr. .Any({{UniS32, _, UniS32}, {{}, {Sgpr32, None, Vgpr32}}}); + addRulesForIOpcs({amdgcn_s_setprio, amdgcn_s_sethalt, amdgcn_s_nop}) + .Any({{}, {{}, {IntrId, Imm}}}); + addRulesForIOpcs({amdgcn_s_sleep}).Any({{_, _}, {{}, {IntrId, Imm}}}); addRulesForIOpcs({amdgcn_bitop3}, Standard) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll index 24fdb5d661b0..173e8202f205 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @test_s_nop() { ; GCN-LABEL: test_s_nop: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll index 34258d6c5f36..d9dcea46debc 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @test_s_sethalt() { ; GCN-LABEL: test_s_sethalt: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll index 8282ff3ed2fc..79d4f28254da 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn -show-mc-encoding < %s | FileCheck -check-prefix=SI %s -; RUN: llc -global-isel -mtriple=amdgcn -show-mc-encoding < %s | FileCheck -check-prefix=SI %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -show-mc-encoding < %s | FileCheck -check-prefix=SI %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx90a -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 %s declare void @llvm.amdgcn.s.setprio(i16) #0