AMDGPU: Add baseline test for treating v_pk_mov_b32 like reg_sequence (#125656)
This commit is contained in:
Matt Arsenault
GitHub
parent
0b0f3da6a8
commit
eef0205345
413
llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
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413
llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
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@ -0,0 +1,413 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=peephole-opt -o - %s | FileCheck %s
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_1_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_1_0
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]], 8, [[REG_SEQUENCE]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY2]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY3]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%3:vreg_64_align2 = V_PK_MOV_B32 12, %2, 8, %2, 0, 0, 0, 0, 0, implicit $exec
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%4:vgpr_32 = COPY %3.sub1
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%5:vgpr_32 = COPY %3.sub0
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$vgpr4 = COPY %4
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$vgpr5 = COPY %5
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S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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...
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]], 8, [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY4]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY5]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr2
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%3:vgpr_32 = COPY $vgpr3
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%4:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%5:vreg_64_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
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%6:vreg_64_align2 = V_PK_MOV_B32 12, %4, 8, %5, 0, 0, 0, 0, 0, implicit $exec
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%7:vgpr_32 = COPY %6.sub1
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%8:vgpr_32 = COPY %6.sub0
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$vgpr4 = COPY %7
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$vgpr5 = COPY %8
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S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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...
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_sgpr_sgpr_1_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr8, $sgpr9
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_sgpr_sgpr_1_0
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; CHECK: liveins: $sgpr8, $sgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]], 8, [[REG_SEQUENCE]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY2]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY3]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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%0:sreg_32 = COPY $sgpr8
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%1:sreg_32 = COPY $sgpr9
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%2:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%3:vreg_64_align2 = V_PK_MOV_B32 12, %2, 8, %2, 0, 0, 0, 0, 0, implicit $exec
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%4:vgpr_32 = COPY %3.sub1
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%5:vgpr_32 = COPY %3.sub0
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$vgpr4 = COPY %4
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$vgpr5 = COPY %5
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S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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...
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_sgpr_3_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr8, $vgpr9, $sgpr10, $sgpr11
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_sgpr_3_0
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; CHECK: liveins: $vgpr8, $vgpr9, $sgpr10, $sgpr11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr9
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr10
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr11
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]], 8, [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY4]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY5]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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%0:vgpr_32 = COPY $vgpr8
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%1:vgpr_32 = COPY $vgpr9
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%2:sreg_64 = COPY $sgpr10
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%3:sreg_64 = COPY $sgpr11
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%4:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%5:sreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
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%6:vreg_64_align2 = V_PK_MOV_B32 12, %4, 8, %5, 0, 0, 0, 0, 0, implicit $exec
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%7:vgpr_32 = COPY %6.sub1
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%8:vgpr_32 = COPY %6.sub0
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$vgpr4 = COPY %7
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$vgpr5 = COPY %8
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S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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...
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_sgpr_vgpr_3_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr8, $sgpr9, $vgpr10, $vgpr11
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_sgpr_vgpr_3_0
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; CHECK: liveins: $sgpr8, $sgpr9, $vgpr10, $vgpr11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr10
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr11
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]], 8, [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY4]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY5]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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%0:sreg_32 = COPY $sgpr8
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%1:sreg_32 = COPY $sgpr9
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%2:vgpr_32 = COPY $vgpr10
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%3:vgpr_32 = COPY $vgpr11
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%4:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%5:vreg_64_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
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%6:vreg_64_align2 = V_PK_MOV_B32 12, %4, 8, %5, 0, 0, 0, 0, 0, implicit $exec
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%7:vgpr_32 = COPY %6.sub1
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%8:vgpr_32 = COPY %6.sub0
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$vgpr4 = COPY %7
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$vgpr5 = COPY %8
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S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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...
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_undef_lhs
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_undef_lhs
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, undef [[REG_SEQUENCE]], 8, [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY4]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY5]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr2
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%3:vgpr_32 = COPY $vgpr3
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%4:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%5:vreg_64_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
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%6:vreg_64_align2 = V_PK_MOV_B32 12, undef %4, 8, %5, 0, 0, 0, 0, 0, implicit $exec
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%7:vgpr_32 = COPY %6.sub1
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%8:vgpr_32 = COPY %6.sub0
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$vgpr4 = COPY %7
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$vgpr5 = COPY %8
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S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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...
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_undef_rhs
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_undef_rhs
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]], 8, undef [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY4]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY5]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr2
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%3:vgpr_32 = COPY $vgpr3
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%4:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%5:vreg_64_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
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%6:vreg_64_align2 = V_PK_MOV_B32 12, %4, 8, undef %5, 0, 0, 0, 0, 0, implicit $exec
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%7:vgpr_32 = COPY %6.sub1
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%8:vgpr_32 = COPY %6.sub0
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$vgpr4 = COPY %7
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$vgpr5 = COPY %8
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S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
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...
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---
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name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_undef_undef
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_undef_undef
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, undef [[REG_SEQUENCE]], 8, undef [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
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; CHECK-NEXT: $vgpr4 = COPY [[COPY4]]
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; CHECK-NEXT: $vgpr5 = COPY [[COPY5]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
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%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = COPY $vgpr2
|
||||
%3:vgpr_32 = COPY $vgpr3
|
||||
%4:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
|
||||
%5:vreg_64_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
|
||||
%6:vreg_64_align2 = V_PK_MOV_B32 12, undef %4, 8, undef %5, 0, 0, 0, 0, 0, implicit $exec
|
||||
%7:vgpr_32 = COPY %6.sub1
|
||||
%8:vgpr_32 = COPY %6.sub0
|
||||
$vgpr4 = COPY %7
|
||||
$vgpr5 = COPY %8
|
||||
S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_compose_src_subregs_0
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
|
||||
|
||||
; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_3_0_compose_src_subregs_0
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
|
||||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
|
||||
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
|
||||
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2
|
||||
; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]].sub0_sub1, 8, [[REG_SEQUENCE1]].sub0_sub1, 0, 0, 0, 0, 0, implicit $exec
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
|
||||
; CHECK-NEXT: $vgpr4 = COPY [[COPY6]]
|
||||
; CHECK-NEXT: $vgpr5 = COPY [[COPY7]]
|
||||
; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = COPY $vgpr2
|
||||
%3:vgpr_32 = COPY $vgpr3
|
||||
%4:vgpr_32 = COPY $vgpr4
|
||||
%5:vgpr_32 = COPY $vgpr5
|
||||
%6:vreg_96_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2
|
||||
%7:vreg_96_align2 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1, %5, %subreg.sub2
|
||||
%8:vreg_64_align2 = V_PK_MOV_B32 12, %6.sub0_sub1, 8, %7.sub0_sub1, 0, 0, 0, 0, 0, implicit $exec
|
||||
%9:vgpr_32 = COPY %8.sub1
|
||||
%10:vgpr_32 = COPY %8.sub0
|
||||
$vgpr4 = COPY %9
|
||||
$vgpr5 = COPY %10
|
||||
S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_0_3_compose_src_subregs_0
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
|
||||
|
||||
; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_0_3_compose_src_subregs_0
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
|
||||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
|
||||
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
|
||||
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2
|
||||
; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, [[REG_SEQUENCE]].sub0_sub1, 12, [[REG_SEQUENCE1]].sub0_sub1, 0, 0, 0, 0, 0, implicit $exec
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
|
||||
; CHECK-NEXT: $vgpr4 = COPY [[COPY6]]
|
||||
; CHECK-NEXT: $vgpr5 = COPY [[COPY7]]
|
||||
; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = COPY $vgpr2
|
||||
%3:vgpr_32 = COPY $vgpr3
|
||||
%4:vgpr_32 = COPY $vgpr4
|
||||
%5:vgpr_32 = COPY $vgpr5
|
||||
%6:vreg_96_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2
|
||||
%7:vreg_96_align2 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1, %5, %subreg.sub2
|
||||
%8:vreg_64_align2 = V_PK_MOV_B32 8, %6.sub0_sub1, 12, %7.sub0_sub1, 0, 0, 0, 0, 0, implicit $exec
|
||||
%9:vgpr_32 = COPY %8.sub1
|
||||
%10:vgpr_32 = COPY %8.sub0
|
||||
$vgpr4 = COPY %9
|
||||
$vgpr5 = COPY %10
|
||||
S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_compose_src_subregs_1
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
|
||||
|
||||
; CHECK-LABEL: name: v_pk_mov_b32__reg_sequence_shuffle_vgpr_vgpr_compose_src_subregs_1
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
|
||||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7
|
||||
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
|
||||
; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 12, [[REG_SEQUENCE]].sub2_sub3, 12, [[REG_SEQUENCE1]].sub0_sub1, 0, 0, 0, 0, 0, implicit $exec
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub1
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[V_PK_MOV_B32_]].sub0
|
||||
; CHECK-NEXT: $vgpr4 = COPY [[COPY8]]
|
||||
; CHECK-NEXT: $vgpr5 = COPY [[COPY9]]
|
||||
; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = COPY $vgpr2
|
||||
%3:vgpr_32 = COPY $vgpr3
|
||||
%4:vgpr_32 = COPY $vgpr4
|
||||
%5:vgpr_32 = COPY $vgpr5
|
||||
%6:vgpr_32 = COPY $vgpr6
|
||||
%7:vgpr_32 = COPY $vgpr7
|
||||
%8:vreg_128_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%9:vreg_128_align2 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1, %6, %subreg.sub2, %7, %subreg.sub3
|
||||
%10:vreg_64_align2 = V_PK_MOV_B32 12, %8.sub2_sub3, 12, %9.sub0_sub1, 0, 0, 0, 0, 0, implicit $exec
|
||||
%11:vgpr_32 = COPY %10.sub1
|
||||
%12:vgpr_32 = COPY %10.sub0
|
||||
$vgpr4 = COPY %11
|
||||
$vgpr5 = COPY %12
|
||||
S_ENDPGM 0, implicit $vgpr4, implicit $vgpr5
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user