[AMDGPU] gfx1250 intrinscs codegen tests update. NFC (#155312)
This commit is contained in:
Stanislav Mekhanoshin
GitHub
parent
68107bb360
commit
f13a35c447
@ -2,6 +2,7 @@
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -o - < %s | FileCheck %s --check-prefixes=GFX,GFX6
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -o - < %s | FileCheck %s --check-prefixes=GFX,GFX8
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX10
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX1250
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declare i16 @llvm.abs.i16(i16, i1)
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declare i32 @llvm.abs.i32(i32, i1)
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@ -13,11 +14,30 @@ declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)
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declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
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define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
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; GFX-LABEL: abs_sgpr_i16:
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; GFX: ; %bb.0:
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; GFX-NEXT: s_sext_i32_i16 s0, s0
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; GFX-NEXT: s_abs_i32 s0, s0
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; GFX-NEXT: ; return to shader part epilog
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; GFX6-LABEL: abs_sgpr_i16:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_sext_i32_i16 s0, s0
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; GFX6-NEXT: s_abs_i32 s0, s0
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; GFX6-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: abs_sgpr_i16:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_sext_i32_i16 s0, s0
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; GFX8-NEXT: s_abs_i32 s0, s0
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: abs_sgpr_i16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_sext_i32_i16 s0, s0
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; GFX10-NEXT: s_abs_i32 s0, s0
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_sgpr_i16:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_sext_i32_i16 s0, s0
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-NEXT: s_abs_i32 s0, s0
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
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ret i16 %res
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}
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@ -32,14 +52,42 @@ define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {
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}
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define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
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; GFX-LABEL: abs_sgpr_i64:
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; GFX: ; %bb.0:
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; GFX-NEXT: s_ashr_i32 s2, s1, 31
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; GFX-NEXT: s_add_u32 s0, s0, s2
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; GFX-NEXT: s_mov_b32 s3, s2
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; GFX-NEXT: s_addc_u32 s1, s1, s2
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; GFX-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
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; GFX-NEXT: ; return to shader part epilog
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; GFX6-LABEL: abs_sgpr_i64:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_ashr_i32 s2, s1, 31
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; GFX6-NEXT: s_add_u32 s0, s0, s2
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; GFX6-NEXT: s_mov_b32 s3, s2
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; GFX6-NEXT: s_addc_u32 s1, s1, s2
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; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
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; GFX6-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: abs_sgpr_i64:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_ashr_i32 s2, s1, 31
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; GFX8-NEXT: s_add_u32 s0, s0, s2
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; GFX8-NEXT: s_mov_b32 s3, s2
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; GFX8-NEXT: s_addc_u32 s1, s1, s2
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; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: abs_sgpr_i64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_ashr_i32 s2, s1, 31
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; GFX10-NEXT: s_add_u32 s0, s0, s2
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; GFX10-NEXT: s_mov_b32 s3, s2
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; GFX10-NEXT: s_addc_u32 s1, s1, s2
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; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_sgpr_i64:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_ashr_i32 s2, s1, 31
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX1250-NEXT: s_mov_b32 s3, s2
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; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
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ret i64 %res
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}
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@ -78,6 +126,14 @@ define amdgpu_cs i16 @abs_vgpr_i16(i16 %arg) {
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; GFX10-NEXT: v_max_i16 v0, v0, v1
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; GFX10-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_i16:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u16 v1, 0, v0
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_max_i16 v0, v0, v1
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
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ret i16 %res
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}
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@ -103,6 +159,14 @@ define amdgpu_cs i32 @abs_vgpr_i32(i32 %arg) {
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; GFX10-NEXT: v_max_i32_e32 v0, v0, v1
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; GFX10-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_i32:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u32_e32 v1, 0, v0
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_max_i32_e32 v0, v0, v1
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
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ret i32 %res
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}
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@ -140,6 +204,20 @@ define amdgpu_cs i64 @abs_vgpr_i64(i64 %arg) {
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; GFX10-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10-NEXT: v_readfirstlane_b32 s1, v1
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_i64:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_mov_b32_e32 v3, v2
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; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX1250-NEXT: v_xor_b32_e32 v1, v1, v2
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
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ret i64 %res
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}
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@ -192,6 +270,24 @@ define amdgpu_cs <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
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; GFX10-NEXT: v_readfirstlane_b32 s2, v2
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; GFX10-NEXT: v_readfirstlane_b32 s3, v3
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_v4i32:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_dual_sub_nc_u32 v4, 0, v0 :: v_dual_sub_nc_u32 v5, 0, v1
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; GFX1250-NEXT: v_dual_sub_nc_u32 v6, 0, v2 :: v_dual_sub_nc_u32 v7, 0, v3
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
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; GFX1250-NEXT: v_max_i32_e32 v0, v0, v4
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; GFX1250-NEXT: v_max_i32_e32 v1, v1, v5
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
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; GFX1250-NEXT: v_max_i32_e32 v2, v2, v6
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; GFX1250-NEXT: v_max_i32_e32 v3, v3, v7
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
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; GFX1250-NEXT: v_readfirstlane_b32 s2, v2
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; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
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ret <4 x i32> %res
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}
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@ -243,6 +339,21 @@ define amdgpu_cs <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {
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; GFX10-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10-NEXT: v_readfirstlane_b32 s1, v1
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_v2i8:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 8
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; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 8
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-NEXT: v_sub_nc_u16 v2, 0, v0
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; GFX1250-NEXT: v_sub_nc_u16 v3, 0, v1
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-NEXT: v_max_i16 v0, v0, v2
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; GFX1250-NEXT: v_max_i16 v1, v1, v3
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
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ret <2 x i8> %res
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}
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@ -307,6 +418,27 @@ define amdgpu_cs <3 x i8> @abs_vgpr_v3i8(<3 x i8> %arg) {
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; GFX10-NEXT: v_readfirstlane_b32 s1, v1
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; GFX10-NEXT: v_readfirstlane_b32 s2, v2
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_v3i8:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 8
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; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 8
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; GFX1250-NEXT: v_bfe_i32 v2, v2, 0, 8
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
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; GFX1250-NEXT: v_sub_nc_u16 v3, 0, v0
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; GFX1250-NEXT: v_sub_nc_u16 v4, 0, v1
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
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; GFX1250-NEXT: v_sub_nc_u16 v5, 0, v2
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; GFX1250-NEXT: v_max_i16 v0, v0, v3
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
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; GFX1250-NEXT: v_max_i16 v1, v1, v4
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; GFX1250-NEXT: v_max_i16 v2, v2, v5
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3)
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; GFX1250-NEXT: v_readfirstlane_b32 s2, v2
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
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ret <3 x i8> %res
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}
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@ -341,6 +473,16 @@ define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {
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; GFX10-NEXT: s_abs_i32 s0, s0
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; GFX10-NEXT: s_pack_ll_b32_b16 s0, s1, s0
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_sgpr_v2i16:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_sext_i32_i16 s1, s0
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; GFX1250-NEXT: s_ashr_i32 s0, s0, 16
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; GFX1250-NEXT: s_abs_i32 s1, s1
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; GFX1250-NEXT: s_abs_i32 s0, s0
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s1, s0
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
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ret <2 x i16> %res
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}
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@ -375,6 +517,14 @@ define amdgpu_cs <2 x i16> @abs_vgpr_v2i16(<2 x i16> %arg) {
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; GFX10-NEXT: v_pk_max_i16 v0, v0, v1
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; GFX10-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_v2i16:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_pk_sub_i16 v1, 0, v0
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; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_pk_max_i16 v0, v0, v1
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
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ret <2 x i16> %res
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}
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@ -416,6 +566,17 @@ define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {
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; GFX10-NEXT: s_pack_ll_b32_b16 s0, s2, s0
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; GFX10-NEXT: s_abs_i32 s1, s1
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_sgpr_v3i16:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_sext_i32_i16 s2, s0
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; GFX1250-NEXT: s_ashr_i32 s0, s0, 16
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; GFX1250-NEXT: s_abs_i32 s2, s2
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; GFX1250-NEXT: s_abs_i32 s0, s0
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; GFX1250-NEXT: s_sext_i32_i16 s1, s1
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; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s2, s0
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; GFX1250-NEXT: s_abs_i32 s1, s1
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; GFX1250-NEXT: ; return to shader part epilog
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%res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
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ret <3 x i16> %res
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}
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@ -460,6 +621,18 @@ define amdgpu_cs <3 x i16> @abs_vgpr_v3i16(<3 x i16> %arg) {
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; GFX10-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10-NEXT: v_readfirstlane_b32 s1, v1
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: abs_vgpr_v3i16:
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; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: v_pk_sub_i16 v2, 0, v0
|
||||
; GFX1250-NEXT: v_sub_nc_u16 v3, 0, v1
|
||||
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
||||
; GFX1250-NEXT: v_pk_max_i16 v0, v0, v2
|
||||
; GFX1250-NEXT: v_max_i16 v1, v1, v3
|
||||
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
||||
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
|
||||
; GFX1250-NEXT: ; return to shader part epilog
|
||||
%res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
|
||||
ret <3 x i16> %res
|
||||
}
|
||||
|
||||
@ -2,10 +2,12 @@
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,CI-SDAG %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,CI-GISEL %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
|
||||
|
||||
define amdgpu_kernel void @is_local_vgpr(ptr addrspace(1) %ptr.ptr) {
|
||||
; CIT-LABEL: is_local_vgpr:
|
||||
@ -90,6 +92,21 @@ define amdgpu_kernel void @is_local_vgpr(ptr addrspace(1) %ptr.ptr) {
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v0, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-LABEL: is_local_vgpr:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
||||
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
||||
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-NEXT: global_load_b64 v[0:1], v0, s[0:1] scale_offset scope:SCOPE_SYS
|
||||
; GFX1250-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX1250-NEXT: s_wait_xcnt 0x0
|
||||
; GFX1250-NEXT: s_mov_b64 s[0:1], src_shared_base
|
||||
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v1
|
||||
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
||||
; GFX1250-NEXT: global_store_b32 v[0:1], v0, off
|
||||
; GFX1250-NEXT: s_endpgm
|
||||
;
|
||||
; CI-GISEL-LABEL: is_local_vgpr:
|
||||
; CI-GISEL: ; %bb.0:
|
||||
; CI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
||||
@ -237,6 +254,23 @@ define amdgpu_kernel void @is_local_sgpr(ptr %ptr) {
|
||||
; GFX9-SDAG-NEXT: .LBB1_2: ; %bb1
|
||||
; GFX9-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-SDAG-LABEL: is_local_sgpr:
|
||||
; GFX1250-SDAG: ; %bb.0:
|
||||
; GFX1250-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x4
|
||||
; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], src_shared_base
|
||||
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s2, s1
|
||||
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, -1, 0
|
||||
; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX1250-SDAG-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
||||
; GFX1250-SDAG-NEXT: s_cbranch_vccnz .LBB1_2
|
||||
; GFX1250-SDAG-NEXT: ; %bb.1: ; %bb0
|
||||
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS
|
||||
; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0
|
||||
; GFX1250-SDAG-NEXT: .LBB1_2: ; %bb1
|
||||
; GFX1250-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; CI-GISEL-LABEL: is_local_sgpr:
|
||||
; CI-GISEL: ; %bb.0:
|
||||
; CI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
||||
@ -296,6 +330,20 @@ define amdgpu_kernel void @is_local_sgpr(ptr %ptr) {
|
||||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: .LBB1_2: ; %bb1
|
||||
; GFX11-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-GISEL-LABEL: is_local_sgpr:
|
||||
; GFX1250-GISEL: ; %bb.0:
|
||||
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
||||
; GFX1250-GISEL-NEXT: s_mov_b64 s[2:3], src_shared_base
|
||||
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-GISEL-NEXT: s_cmp_lg_u32 s1, s3
|
||||
; GFX1250-GISEL-NEXT: s_cbranch_scc1 .LBB1_2
|
||||
; GFX1250-GISEL-NEXT: ; %bb.1: ; %bb0
|
||||
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS
|
||||
; GFX1250-GISEL-NEXT: s_wait_storecnt 0x0
|
||||
; GFX1250-GISEL-NEXT: .LBB1_2: ; %bb1
|
||||
; GFX1250-GISEL-NEXT: s_endpgm
|
||||
%val = call i1 @llvm.amdgcn.is.shared(ptr %ptr)
|
||||
br i1 %val, label %bb0, label %bb1
|
||||
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11,GFX11-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11,GFX11-GISEL %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL %s
|
||||
|
||||
define amdgpu_kernel void @test_get_doorbell(ptr addrspace(1) %out) {
|
||||
; GFX11-SDAG-LABEL: test_get_doorbell:
|
||||
@ -20,6 +22,24 @@ define amdgpu_kernel void @test_get_doorbell(ptr addrspace(1) %out) {
|
||||
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-SDAG-LABEL: test_get_doorbell:
|
||||
; GFX1250-SDAG: ; %bb.0:
|
||||
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DOORBELL)
|
||||
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
|
||||
; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
|
||||
; GFX1250-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-GISEL-LABEL: test_get_doorbell:
|
||||
; GFX1250-GISEL: ; %bb.0:
|
||||
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DOORBELL)
|
||||
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX1250-GISEL-NEXT: s_endpgm
|
||||
%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 128)
|
||||
store i32 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -43,6 +63,24 @@ define amdgpu_kernel void @test_get_ddid(ptr addrspace(1) %out) {
|
||||
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-SDAG-LABEL: test_get_ddid:
|
||||
; GFX1250-SDAG: ; %bb.0:
|
||||
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DDID)
|
||||
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
|
||||
; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
|
||||
; GFX1250-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-GISEL-LABEL: test_get_ddid:
|
||||
; GFX1250-GISEL: ; %bb.0:
|
||||
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DDID)
|
||||
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX1250-GISEL-NEXT: s_endpgm
|
||||
%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 129)
|
||||
store i32 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -58,6 +96,16 @@ define amdgpu_kernel void @test_get_tma(ptr addrspace(1) %out) {
|
||||
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
||||
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX11-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-LABEL: test_get_tma:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TMA)
|
||||
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
|
||||
; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX1250-NEXT: s_endpgm
|
||||
%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 130)
|
||||
store i64 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -73,6 +121,16 @@ define amdgpu_kernel void @test_get_realtime(ptr addrspace(1) %out) {
|
||||
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
||||
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX11-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-LABEL: test_get_realtime:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
|
||||
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
|
||||
; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX1250-NEXT: s_endpgm
|
||||
%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 131)
|
||||
store i64 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -96,6 +154,24 @@ define amdgpu_kernel void @test_savewave(ptr addrspace(1) %out) {
|
||||
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-SDAG-LABEL: test_savewave:
|
||||
; GFX1250-SDAG: ; %bb.0:
|
||||
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_SAVE_WAVE)
|
||||
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
|
||||
; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
|
||||
; GFX1250-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-GISEL-LABEL: test_savewave:
|
||||
; GFX1250-GISEL: ; %bb.0:
|
||||
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_SAVE_WAVE)
|
||||
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX1250-GISEL-NEXT: s_endpgm
|
||||
%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 132)
|
||||
store i32 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -111,6 +187,16 @@ define amdgpu_kernel void @test_get_tba(ptr addrspace(1) %out) {
|
||||
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
||||
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX11-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-LABEL: test_get_tba:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TBA)
|
||||
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
|
||||
; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX1250-NEXT: s_endpgm
|
||||
%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 133)
|
||||
store i64 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -134,6 +220,24 @@ define amdgpu_kernel void @test_get_0_i32(ptr addrspace(1) %out) {
|
||||
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-SDAG-LABEL: test_get_0_i32:
|
||||
; GFX1250-SDAG: ; %bb.0:
|
||||
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(0, 0, 0)
|
||||
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
|
||||
; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
|
||||
; GFX1250-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-GISEL-LABEL: test_get_0_i32:
|
||||
; GFX1250-GISEL: ; %bb.0:
|
||||
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(0, 0, 0)
|
||||
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
|
||||
; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX1250-GISEL-NEXT: s_endpgm
|
||||
%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 0)
|
||||
store i32 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -149,6 +253,16 @@ define amdgpu_kernel void @test_get_99999_i64(ptr addrspace(1) %out) {
|
||||
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
||||
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX11-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-LABEL: test_get_99999_i64:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], 99999
|
||||
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
|
||||
; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX1250-NEXT: s_endpgm
|
||||
%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 99999)
|
||||
store i64 %ret, ptr addrspace(1) %out
|
||||
ret void
|
||||
|
||||
@ -3,8 +3,10 @@
|
||||
; RUN: not llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s 2>&1 | FileCheck -check-prefix=GFX9-GISEL-ERR %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 < %s | FileCheck -check-prefix=GFX9 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX9 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefix=GFX12 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX12 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefix=GFX1200 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX1200 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -global-isel=0 < %s | FileCheck -check-prefix=GFX1250 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX1250 %s
|
||||
|
||||
; GFX9-SDAG-ERR: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.wave.id
|
||||
; GFX9-GISEL-ERR: LLVM ERROR: unable to legalize instruction: {{.*}} = G_INTRINSIC intrinsic(@llvm.amdgcn.wave.id)
|
||||
@ -17,13 +19,21 @@ define amdgpu_cs void @test_wave_id(ptr addrspace(1) %out) {
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX12-LABEL: test_wave_id:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
|
||||
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
|
||||
; GFX12-NEXT: s_endpgm
|
||||
; GFX1200-LABEL: test_wave_id:
|
||||
; GFX1200: ; %bb.0:
|
||||
; GFX1200-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
|
||||
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX1200-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX1200-NEXT: global_store_b32 v[0:1], v2, off
|
||||
; GFX1200-NEXT: s_endpgm
|
||||
;
|
||||
; GFX1250-LABEL: test_wave_id:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
|
||||
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
|
||||
; GFX1250-NEXT: s_endpgm
|
||||
%waveid = call i32 @llvm.amdgcn.wave.id()
|
||||
store i32 %waveid, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -39,6 +49,28 @@ define amdgpu_gfx void @test_wave_id_callable(ptr addrspace(1) %out) {
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX1200-LABEL: test_wave_id_callable:
|
||||
; GFX1200: ; %bb.0:
|
||||
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX1200-NEXT: s_wait_expcnt 0x0
|
||||
; GFX1200-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX1200-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX1200-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1200-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
|
||||
; GFX1200-NEXT: s_wait_alu 0xfffe
|
||||
; GFX1200-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX1200-NEXT: global_store_b32 v[0:1], v2, off
|
||||
; GFX1200-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX1250-LABEL: test_wave_id_callable:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX1250-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
|
||||
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
|
||||
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
|
||||
; GFX12-LABEL: test_wave_id_callable:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user