diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 49a681efc79c..a3b64aee297b 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1357,17 +1357,10 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
         // DsCnt corresponds to LGKMCnt here.
         return (Decoded.DsCnt == 0);
       }
-      case AMDGPU::S_WAIT_STORECNT:
-      case AMDGPU::S_WAIT_STORECNT_DSCNT:
-      case AMDGPU::S_WAIT_LOADCNT:
-      case AMDGPU::S_WAIT_LOADCNT_DSCNT:
-      case AMDGPU::S_WAIT_SAMPLECNT:
-      case AMDGPU::S_WAIT_BVHCNT:
-      case AMDGPU::S_WAIT_DSCNT:
-      case AMDGPU::S_WAIT_EXPCNT:
-      case AMDGPU::S_WAIT_KMCNT:
-        llvm_unreachable("unexpected wait count instruction");
       default:
+        assert((!SIInstrInfo::isWaitcnt(MI.getOpcode()) ||
+                MI.getOpcode() == AMDGPU::S_WAIT_IDLE) &&
+               "unexpected wait count instruction");
         // SOPP instructions cannot mitigate the hazard.
         if (TII->isSOPP(MI))
           return false;
@@ -2257,28 +2250,7 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
     if (WaitStates >= 3 || SIInstrInfo::isVALU(MI))
       return true;
 
-    switch (MI.getOpcode()) {
-    case AMDGPU::S_WAITCNT:
-    case AMDGPU::S_WAITCNT_VSCNT:
-    case AMDGPU::S_WAITCNT_VMCNT:
-    case AMDGPU::S_WAITCNT_EXPCNT:
-    case AMDGPU::S_WAITCNT_LGKMCNT:
-    case AMDGPU::S_WAIT_IDLE:
-    case AMDGPU::S_WAIT_LOADCNT:
-    case AMDGPU::S_WAIT_LOADCNT_DSCNT:
-    case AMDGPU::S_WAIT_SAMPLECNT:
-    case AMDGPU::S_WAIT_BVHCNT:
-    case AMDGPU::S_WAIT_STORECNT:
-    case AMDGPU::S_WAIT_STORECNT_DSCNT:
-    case AMDGPU::S_WAIT_EXPCNT:
-    case AMDGPU::S_WAIT_DSCNT:
-    case AMDGPU::S_WAIT_KMCNT:
-      return true;
-    default:
-      break;
-    }
-
-    return false;
+    return SIInstrInfo::isWaitcnt(MI.getOpcode());
   };
 
   return FPAtomicToDenormModeWaitStates -
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 18f0e5b9b56b..5cbf6f5ab045 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1056,7 +1056,7 @@ public:
     }
   }
 
-  bool isWaitcnt(unsigned Opcode) const {
+  static bool isWaitcnt(unsigned Opcode) {
     switch (getNonSoftWaitcntOpcode(Opcode)) {
     case AMDGPU::S_WAITCNT:
     case AMDGPU::S_WAITCNT_VSCNT: