[AArch64] Codegen for FEAT_LSE128
Codegen support for 128-bit atomicrmw (and|or|xchg).
- store atomic -> swpp
- atomicrmw xchg -> swpp
- atomicrmw and -> ldclrp
- atomicrmw or -> ldsetp
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D141406
This commit is contained in:
Tomas Matheson
parent
f4a6842c5a
commit
f1f583347d
@ -821,6 +821,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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#undef LCALLNAME5
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}
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if (Subtarget->hasLSE128()) {
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// Custom lowering because i128 is not legal. Must be replaced by 2x64
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// values. ATOMIC_LOAD_AND also needs op legalisation to emit LDCLRP.
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setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i128, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i128, Custom);
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i128, Custom);
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}
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// 128-bit loads and stores can be done without expanding
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setOperationAction(ISD::LOAD, MVT::i128, Custom);
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setOperationAction(ISD::STORE, MVT::i128, Custom);
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@ -13301,12 +13309,14 @@ SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op,
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SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op,
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SelectionDAG &DAG) const {
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auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
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// No point replacing if we don't have the relevant instruction/libcall anyway
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if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics())
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return SDValue();
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// LSE has an atomic load-clear instruction, but not a load-and.
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SDLoc dl(Op);
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MVT VT = Op.getSimpleValueType();
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assert(VT != MVT::i128 && "Handled elsewhere, code replicated.");
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SDValue RHS = Op.getOperand(2);
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AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode());
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RHS = DAG.getNode(ISD::XOR, dl, VT, DAG.getConstant(-1ULL, dl, VT), RHS);
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@ -22082,6 +22092,137 @@ static void ReplaceCMP_SWAP_128Results(SDNode *N,
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Results.push_back(SDValue(CmpSwap, 3));
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}
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static unsigned getAtomicLoad128Opcode(unsigned ISDOpcode,
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AtomicOrdering Ordering) {
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// ATOMIC_LOAD_CLR only appears when lowering ATOMIC_LOAD_AND (see
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// LowerATOMIC_LOAD_AND). We can't take that approach with 128-bit, because
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// the type is not legal. Therefore we shouldn't expect to see a 128-bit
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// ATOMIC_LOAD_CLR at any point.
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assert(ISDOpcode != ISD::ATOMIC_LOAD_CLR &&
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"ATOMIC_LOAD_AND should be lowered to LDCLRP directly");
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assert(ISDOpcode != ISD::ATOMIC_LOAD_ADD && "There is no 128 bit LDADD");
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assert(ISDOpcode != ISD::ATOMIC_LOAD_SUB && "There is no 128 bit LDSUB");
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if (ISDOpcode == ISD::ATOMIC_LOAD_AND) {
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// The operand will need to be XORed in a separate step.
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switch (Ordering) {
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case AtomicOrdering::Monotonic:
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return AArch64::LDCLRP;
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break;
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case AtomicOrdering::Acquire:
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return AArch64::LDCLRPA;
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break;
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case AtomicOrdering::Release:
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return AArch64::LDCLRPL;
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break;
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case AtomicOrdering::AcquireRelease:
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case AtomicOrdering::SequentiallyConsistent:
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return AArch64::LDCLRPAL;
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break;
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default:
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llvm_unreachable("Unexpected ordering!");
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}
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}
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if (ISDOpcode == ISD::ATOMIC_LOAD_OR) {
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switch (Ordering) {
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case AtomicOrdering::Monotonic:
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return AArch64::LDSETP;
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break;
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case AtomicOrdering::Acquire:
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return AArch64::LDSETPA;
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break;
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case AtomicOrdering::Release:
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return AArch64::LDSETPL;
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break;
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case AtomicOrdering::AcquireRelease:
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case AtomicOrdering::SequentiallyConsistent:
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return AArch64::LDSETPAL;
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break;
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default:
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llvm_unreachable("Unexpected ordering!");
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}
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}
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if (ISDOpcode == ISD::ATOMIC_SWAP) {
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switch (Ordering) {
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case AtomicOrdering::Monotonic:
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return AArch64::SWPP;
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break;
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case AtomicOrdering::Acquire:
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return AArch64::SWPPA;
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break;
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case AtomicOrdering::Release:
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return AArch64::SWPPL;
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break;
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case AtomicOrdering::AcquireRelease:
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case AtomicOrdering::SequentiallyConsistent:
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return AArch64::SWPPAL;
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break;
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default:
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llvm_unreachable("Unexpected ordering!");
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}
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}
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llvm_unreachable("Unexpected ISDOpcode!");
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}
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static void ReplaceATOMIC_LOAD_128Results(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG,
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const AArch64Subtarget *Subtarget) {
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// LSE128 has a 128-bit RMW ops, but i128 is not a legal type, so lower it
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// here. This follows the approach of the CMP_SWAP_XXX pseudo instructions
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// rather than the CASP instructions, because CASP has register classes for
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// the pairs of registers and therefore uses REG_SEQUENCE and EXTRACT_SUBREG
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// to present them as single operands. LSE128 instructions use the GPR64
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// register class (because the pair does not have to be sequential), like
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// CMP_SWAP_XXX, and therefore we use TRUNCATE and BUILD_PAIR.
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assert(N->getValueType(0) == MVT::i128 &&
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"AtomicLoadXXX on types less than 128 should be legal");
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if (!Subtarget->hasLSE128())
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return;
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MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
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const SDValue &Chain = N->getOperand(0);
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const SDValue &Ptr = N->getOperand(1);
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const SDValue &Val128 = N->getOperand(2);
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std::pair<SDValue, SDValue> Val2x64 = splitInt128(Val128, DAG);
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const unsigned ISDOpcode = N->getOpcode();
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const unsigned MachineOpcode =
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getAtomicLoad128Opcode(ISDOpcode, MemOp->getMergedOrdering());
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if (ISDOpcode == ISD::ATOMIC_LOAD_AND) {
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SDLoc dl(Val128);
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Val2x64.first =
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DAG.getNode(ISD::XOR, dl, MVT::i64,
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DAG.getConstant(-1ULL, dl, MVT::i64), Val2x64.first);
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Val2x64.second =
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DAG.getNode(ISD::XOR, dl, MVT::i64,
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DAG.getConstant(-1ULL, dl, MVT::i64), Val2x64.second);
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}
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SDValue Ops[] = {Val2x64.first, Val2x64.second, Ptr, Chain};
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if (DAG.getDataLayout().isBigEndian())
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std::swap(Ops[0], Ops[1]);
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MachineSDNode *AtomicInst =
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DAG.getMachineNode(MachineOpcode, SDLoc(N),
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DAG.getVTList(MVT::i64, MVT::i64, MVT::Other), Ops);
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DAG.setNodeMemRefs(AtomicInst, {MemOp});
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SDValue Lo = SDValue(AtomicInst, 0), Hi = SDValue(AtomicInst, 1);
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if (DAG.getDataLayout().isBigEndian())
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std::swap(Lo, Hi);
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Results.push_back(DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Lo, Hi));
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Results.push_back(SDValue(AtomicInst, 2)); // Chain out
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}
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void AArch64TargetLowering::ReplaceNodeResults(
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SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
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switch (N->getOpcode()) {
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@ -22135,6 +22276,20 @@ void AArch64TargetLowering::ReplaceNodeResults(
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case ISD::ATOMIC_CMP_SWAP:
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ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);
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return;
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case ISD::ATOMIC_LOAD_CLR:
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assert(N->getValueType(0) != MVT::i128 &&
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"128-bit ATOMIC_LOAD_AND should be lowered directly to LDCLRP");
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break;
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case ISD::ATOMIC_LOAD_AND:
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case ISD::ATOMIC_LOAD_OR:
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case ISD::ATOMIC_SWAP: {
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AtomicSDNode *AN = cast<AtomicSDNode>(N);
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assert(AN->getVal().getValueType() == MVT::i128 &&
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"Expected 128-bit atomicrmw.");
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// These need custom type legalisation so we go directly to instruction.
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ReplaceATOMIC_LOAD_128Results(N, Results, DAG, Subtarget);
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return;
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}
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case ISD::ATOMIC_LOAD:
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case ISD::LOAD: {
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MemSDNode *LoadNode = cast<MemSDNode>(N);
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@ -22368,6 +22523,13 @@ AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
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unsigned Size = AI->getType()->getPrimitiveSizeInBits();
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if (Size > 128) return AtomicExpansionKind::None;
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bool CanUseLSE128 = Subtarget->hasLSE128() && Size == 128 &&
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(AI->getOperation() == AtomicRMWInst::Xchg ||
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AI->getOperation() == AtomicRMWInst::Or ||
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AI->getOperation() == AtomicRMWInst::And);
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if (CanUseLSE128)
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return AtomicExpansionKind::None;
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// Nand is not supported in LSE.
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// Leave 128 bits to LLSC or CmpXChg.
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if (AI->getOperation() != AtomicRMWInst::Nand && Size < 128) {
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@ -116,69 +116,29 @@ define dso_local void @store_atomic_i64_aligned_seq_cst(i64 %value, ptr %ptr) {
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}
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define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr) {
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; -O0-LABEL: store_atomic_i128_aligned_unordered:
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; -O0: casp x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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;
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; -O1-LABEL: store_atomic_i128_aligned_unordered:
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; -O1: ldp x4, x5, [x2]
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; -O1: casp x6, x7, x0, x1, [x2]
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; -O1: cmp x7, x5
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; -O1: ccmp x6, x4, #0, eq
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; CHECK-LABEL: store_atomic_i128_aligned_unordered:
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; CHECK: swpp x0, x1, [x2]
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store atomic i128 %value, ptr %ptr unordered, align 16
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ret void
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}
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define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr) {
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; -O0-LABEL: store_atomic_i128_aligned_monotonic:
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; -O0: casp x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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;
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; -O1-LABEL: store_atomic_i128_aligned_monotonic:
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; -O1: ldp x4, x5, [x2]
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; -O1: casp x6, x7, x0, x1, [x2]
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; -O1: cmp x7, x5
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; -O1: ccmp x6, x4, #0, eq
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; CHECK-LABEL: store_atomic_i128_aligned_monotonic:
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; CHECK: swpp x0, x1, [x2]
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store atomic i128 %value, ptr %ptr monotonic, align 16
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ret void
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}
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define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr) {
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; -O0-LABEL: store_atomic_i128_aligned_release:
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; -O0: caspl x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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;
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; -O1-LABEL: store_atomic_i128_aligned_release:
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; -O1: ldp x4, x5, [x2]
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; -O1: caspl x6, x7, x0, x1, [x2]
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; -O1: cmp x7, x5
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; -O1: ccmp x6, x4, #0, eq
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; CHECK-LABEL: store_atomic_i128_aligned_release:
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; CHECK: swppl x0, x1, [x2]
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store atomic i128 %value, ptr %ptr release, align 16
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ret void
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}
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define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr) {
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; -O0-LABEL: store_atomic_i128_aligned_seq_cst:
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; -O0: caspal x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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;
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; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
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; -O1: ldp x4, x5, [x2]
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; -O1: caspal x6, x7, x0, x1, [x2]
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; -O1: cmp x7, x5
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; -O1: ccmp x6, x4, #0, eq
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; CHECK-LABEL: store_atomic_i128_aligned_seq_cst:
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; CHECK: swppal x0, x1, [x2]
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store atomic i128 %value, ptr %ptr seq_cst, align 16
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ret void
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}
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@ -322,3 +282,6 @@ define dso_local void @store_atomic_i128_unaligned_seq_cst(i128 %value, ptr %ptr
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store atomic i128 %value, ptr %ptr seq_cst, align 1
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ret void
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; -O0: {{.*}}
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; -O1: {{.*}}
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@ -145,85 +145,50 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
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define dso_local i128 @atomicrmw_xchg_i128_aligned_monotonic(ptr %ptr, i128 %value) {
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; -O0-LABEL: atomicrmw_xchg_i128_aligned_monotonic:
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; -O0: casp x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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; -O0: swpp x0, x1, [x8]
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;
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; -O1-LABEL: atomicrmw_xchg_i128_aligned_monotonic:
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; -O1: ldp x4, x5, [x0]
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; -O1: casp x4, x5, x2, x3, [x0]
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; -O1: cmp x5, x7
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; -O1: ccmp x4, x6, #0, eq
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; -O1: swpp x2, x1, [x0]
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%r = atomicrmw xchg ptr %ptr, i128 %value monotonic, align 16
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ret i128 %r
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}
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define dso_local i128 @atomicrmw_xchg_i128_aligned_acquire(ptr %ptr, i128 %value) {
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; -O0-LABEL: atomicrmw_xchg_i128_aligned_acquire:
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; -O0: caspa x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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; -O0: swppa x0, x1, [x8]
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;
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; -O1-LABEL: atomicrmw_xchg_i128_aligned_acquire:
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; -O1: ldp x4, x5, [x0]
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; -O1: caspa x4, x5, x2, x3, [x0]
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; -O1: cmp x5, x7
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; -O1: ccmp x4, x6, #0, eq
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; -O1: swppa x2, x1, [x0]
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%r = atomicrmw xchg ptr %ptr, i128 %value acquire, align 16
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ret i128 %r
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}
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define dso_local i128 @atomicrmw_xchg_i128_aligned_release(ptr %ptr, i128 %value) {
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; -O0-LABEL: atomicrmw_xchg_i128_aligned_release:
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; -O0: caspl x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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; -O0: swppl x0, x1, [x8]
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;
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; -O1-LABEL: atomicrmw_xchg_i128_aligned_release:
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; -O1: ldp x4, x5, [x0]
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; -O1: caspl x4, x5, x2, x3, [x0]
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; -O1: cmp x5, x7
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; -O1: ccmp x4, x6, #0, eq
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; -O1: swppl x2, x1, [x0]
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%r = atomicrmw xchg ptr %ptr, i128 %value release, align 16
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ret i128 %r
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}
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define dso_local i128 @atomicrmw_xchg_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
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; -O0-LABEL: atomicrmw_xchg_i128_aligned_acq_rel:
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; -O0: caspal x0, x1, x2, x3, [x8]
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; -O0: eor x8, x10, x8
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; -O0: eor x11, x9, x11
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; -O0: orr x8, x8, x11
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; -O0: subs x8, x8, #0
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; -O0: swppal x0, x1, [x8]
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;
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; -O1-LABEL: atomicrmw_xchg_i128_aligned_acq_rel:
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; -O1: ldp x4, x5, [x0]
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; -O1: caspal x4, x5, x2, x3, [x0]
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; -O1: cmp x5, x7
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; -O1: ccmp x4, x6, #0, eq
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; -O1: swppal x2, x1, [x0]
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%r = atomicrmw xchg ptr %ptr, i128 %value acq_rel, align 16
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ret i128 %r
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}
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|
||||
define dso_local i128 @atomicrmw_xchg_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_xchg_i128_aligned_seq_cst:
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: swppal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_xchg_i128_aligned_seq_cst:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: caspal x4, x5, x2, x3, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: swppal x2, x1, [x0]
|
||||
%r = atomicrmw xchg ptr %ptr, i128 %value seq_cst, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
@ -1575,105 +1540,70 @@ define dso_local i64 @atomicrmw_and_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_monotonic(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_monotonic:
|
||||
; -O0: and x2, x9, x11
|
||||
; -O0: and x9, x9, x10
|
||||
; -O0: casp x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrp x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_monotonic:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: casp x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrp x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value monotonic, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_acquire(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_acquire:
|
||||
; -O0: and x2, x9, x11
|
||||
; -O0: and x9, x9, x10
|
||||
; -O0: caspa x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpa x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_acquire:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspa x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpa x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value acquire, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_release(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_release:
|
||||
; -O0: and x2, x9, x11
|
||||
; -O0: and x9, x9, x10
|
||||
; -O0: caspl x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpl x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_release:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspl x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpl x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value release, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_acq_rel:
|
||||
; -O0: and x2, x9, x11
|
||||
; -O0: and x9, x9, x10
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_acq_rel:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpal x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value acq_rel, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_seq_cst:
|
||||
; -O0: and x2, x9, x11
|
||||
; -O0: and x9, x9, x10
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_seq_cst:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpal x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value seq_cst, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
@ -2955,105 +2885,50 @@ define dso_local i64 @atomicrmw_or_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_monotonic(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_monotonic:
|
||||
; -O0: orr x2, x9, x11
|
||||
; -O0: orr x9, x9, x10
|
||||
; -O0: casp x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: ldsetp x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_monotonic:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: casp x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: ldsetp x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value monotonic, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_acquire(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_acquire:
|
||||
; -O0: orr x2, x9, x11
|
||||
; -O0: orr x9, x9, x10
|
||||
; -O0: caspa x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: ldsetpa x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_acquire:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspa x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: ldsetpa x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value acquire, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_release(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_release:
|
||||
; -O0: orr x2, x9, x11
|
||||
; -O0: orr x9, x9, x10
|
||||
; -O0: caspl x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: ldsetpl x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_release:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspl x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: ldsetpl x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value release, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_acq_rel:
|
||||
; -O0: orr x2, x9, x11
|
||||
; -O0: orr x9, x9, x10
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: ldsetpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_acq_rel:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: ldsetpal x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value acq_rel, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_seq_cst:
|
||||
; -O0: orr x2, x9, x11
|
||||
; -O0: orr x9, x9, x10
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: eor x8, x10, x8
|
||||
; -O0: eor x11, x9, x11
|
||||
; -O0: orr x8, x8, x11
|
||||
; -O0: subs x8, x8, #0
|
||||
; -O0: ldsetpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_seq_cst:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x5, x7
|
||||
; -O1: ccmp x4, x6, #0, eq
|
||||
; -O1: ldsetpal x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value seq_cst, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
@ -116,61 +116,29 @@ define dso_local void @store_atomic_i64_aligned_seq_cst(i64 %value, ptr %ptr) {
|
||||
}
|
||||
|
||||
define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr) {
|
||||
; -O0-LABEL: store_atomic_i128_aligned_unordered:
|
||||
; -O0: casp x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
;
|
||||
; -O1-LABEL: store_atomic_i128_aligned_unordered:
|
||||
; -O1: ldp x4, x5, [x2]
|
||||
; -O1: casp x6, x7, x0, x1, [x2]
|
||||
; -O1: cmp x6, x4
|
||||
; -O1: ccmp x7, x5, #0, eq
|
||||
; CHECK-LABEL: store_atomic_i128_aligned_unordered:
|
||||
; CHECK: swpp x0, x1, [x2]
|
||||
store atomic i128 %value, ptr %ptr unordered, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr) {
|
||||
; -O0-LABEL: store_atomic_i128_aligned_monotonic:
|
||||
; -O0: casp x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
;
|
||||
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
|
||||
; -O1: ldp x4, x5, [x2]
|
||||
; -O1: casp x6, x7, x0, x1, [x2]
|
||||
; -O1: cmp x6, x4
|
||||
; -O1: ccmp x7, x5, #0, eq
|
||||
; CHECK-LABEL: store_atomic_i128_aligned_monotonic:
|
||||
; CHECK: swpp x0, x1, [x2]
|
||||
store atomic i128 %value, ptr %ptr monotonic, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr) {
|
||||
; -O0-LABEL: store_atomic_i128_aligned_release:
|
||||
; -O0: caspl x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
;
|
||||
; -O1-LABEL: store_atomic_i128_aligned_release:
|
||||
; -O1: ldp x4, x5, [x2]
|
||||
; -O1: caspl x6, x7, x0, x1, [x2]
|
||||
; -O1: cmp x6, x4
|
||||
; -O1: ccmp x7, x5, #0, eq
|
||||
; CHECK-LABEL: store_atomic_i128_aligned_release:
|
||||
; CHECK: swppl x0, x1, [x2]
|
||||
store atomic i128 %value, ptr %ptr release, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr) {
|
||||
; -O0-LABEL: store_atomic_i128_aligned_seq_cst:
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
;
|
||||
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
|
||||
; -O1: ldp x4, x5, [x2]
|
||||
; -O1: caspal x6, x7, x0, x1, [x2]
|
||||
; -O1: cmp x6, x4
|
||||
; -O1: ccmp x7, x5, #0, eq
|
||||
; CHECK-LABEL: store_atomic_i128_aligned_seq_cst:
|
||||
; CHECK: swppal x0, x1, [x2]
|
||||
store atomic i128 %value, ptr %ptr seq_cst, align 16
|
||||
ret void
|
||||
}
|
||||
@ -314,3 +282,6 @@ define dso_local void @store_atomic_i128_unaligned_seq_cst(i128 %value, ptr %ptr
|
||||
store atomic i128 %value, ptr %ptr seq_cst, align 1
|
||||
ret void
|
||||
}
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; -O0: {{.*}}
|
||||
; -O1: {{.*}}
|
||||
|
||||
@ -145,75 +145,50 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
|
||||
|
||||
define dso_local i128 @atomicrmw_xchg_i128_aligned_monotonic(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_xchg_i128_aligned_monotonic:
|
||||
; -O0: casp x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: swpp x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_xchg_i128_aligned_monotonic:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: casp x4, x5, x2, x3, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: swpp x2, x1, [x0]
|
||||
%r = atomicrmw xchg ptr %ptr, i128 %value monotonic, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_xchg_i128_aligned_acquire(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_xchg_i128_aligned_acquire:
|
||||
; -O0: caspa x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: swppa x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_xchg_i128_aligned_acquire:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: caspa x4, x5, x2, x3, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: swppa x2, x1, [x0]
|
||||
%r = atomicrmw xchg ptr %ptr, i128 %value acquire, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_xchg_i128_aligned_release(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_xchg_i128_aligned_release:
|
||||
; -O0: caspl x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: swppl x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_xchg_i128_aligned_release:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: caspl x4, x5, x2, x3, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: swppl x2, x1, [x0]
|
||||
%r = atomicrmw xchg ptr %ptr, i128 %value release, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_xchg_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_xchg_i128_aligned_acq_rel:
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: swppal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_xchg_i128_aligned_acq_rel:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: caspal x4, x5, x2, x3, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: swppal x2, x1, [x0]
|
||||
%r = atomicrmw xchg ptr %ptr, i128 %value acq_rel, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_xchg_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_xchg_i128_aligned_seq_cst:
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: swppal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_xchg_i128_aligned_seq_cst:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: caspal x4, x5, x2, x3, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: swppal x2, x1, [x0]
|
||||
%r = atomicrmw xchg ptr %ptr, i128 %value seq_cst, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
@ -1665,95 +1640,70 @@ define dso_local i64 @atomicrmw_and_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_monotonic(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_monotonic:
|
||||
; -O0: and x2, x11, x12
|
||||
; -O0: and x9, x10, x9
|
||||
; -O0: casp x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrp x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_monotonic:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: casp x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrp x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value monotonic, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_acquire(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_acquire:
|
||||
; -O0: and x2, x11, x12
|
||||
; -O0: and x9, x10, x9
|
||||
; -O0: caspa x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpa x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_acquire:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspa x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpa x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value acquire, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_release(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_release:
|
||||
; -O0: and x2, x11, x12
|
||||
; -O0: and x9, x10, x9
|
||||
; -O0: caspl x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpl x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_release:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspl x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpl x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value release, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_acq_rel:
|
||||
; -O0: and x2, x11, x12
|
||||
; -O0: and x9, x10, x9
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_acq_rel:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpal x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value acq_rel, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_and_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_and_i128_aligned_seq_cst:
|
||||
; -O0: and x2, x11, x12
|
||||
; -O0: and x9, x10, x9
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: mvn x1, x3
|
||||
; -O0: mvn x0, x2
|
||||
; -O0: ldclrpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_and_i128_aligned_seq_cst:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: and x8, x4, x2
|
||||
; -O1: and x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: mvn x1, x3
|
||||
; -O1: mvn x8, x2
|
||||
; -O1: ldclrpal x8, x1, [x0]
|
||||
%r = atomicrmw and ptr %ptr, i128 %value seq_cst, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
@ -3040,95 +2990,50 @@ define dso_local i64 @atomicrmw_or_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_monotonic(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_monotonic:
|
||||
; -O0: orr x2, x11, x12
|
||||
; -O0: orr x9, x10, x9
|
||||
; -O0: casp x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: ldsetp x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_monotonic:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: casp x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: ldsetp x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value monotonic, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_acquire(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_acquire:
|
||||
; -O0: orr x2, x11, x12
|
||||
; -O0: orr x9, x10, x9
|
||||
; -O0: caspa x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: ldsetpa x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_acquire:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspa x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: ldsetpa x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value acquire, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_release(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_release:
|
||||
; -O0: orr x2, x11, x12
|
||||
; -O0: orr x9, x10, x9
|
||||
; -O0: caspl x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: ldsetpl x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_release:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspl x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: ldsetpl x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value release, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_acq_rel:
|
||||
; -O0: orr x2, x11, x12
|
||||
; -O0: orr x9, x10, x9
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: ldsetpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_acq_rel:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: ldsetpal x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value acq_rel, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define dso_local i128 @atomicrmw_or_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
|
||||
; -O0-LABEL: atomicrmw_or_i128_aligned_seq_cst:
|
||||
; -O0: orr x2, x11, x12
|
||||
; -O0: orr x9, x10, x9
|
||||
; -O0: caspal x0, x1, x2, x3, [x8]
|
||||
; -O0: subs x11, x9, x11
|
||||
; -O0: ccmp x8, x10, #0, eq
|
||||
; -O0: ldsetpal x0, x1, [x8]
|
||||
;
|
||||
; -O1-LABEL: atomicrmw_or_i128_aligned_seq_cst:
|
||||
; -O1: ldp x4, x5, [x0]
|
||||
; -O1: orr x8, x4, x2
|
||||
; -O1: orr x9, x7, x3
|
||||
; -O1: caspal x4, x5, x8, x9, [x0]
|
||||
; -O1: cmp x4, x6
|
||||
; -O1: ccmp x5, x7, #0, eq
|
||||
; -O1: ldsetpal x2, x1, [x0]
|
||||
%r = atomicrmw or ptr %ptr, i128 %value seq_cst, align 16
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user