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[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC

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Some of these may eventually need to VirtRegOrUnit.
This commit is contained in:
Craig Topper 2025-01-26 00:15:32 -08:00
parent 37fdde6025
commit f46eb14309
2 changed files with 37 additions and 40 deletions
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51
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
View File

@ -284,10 +284,9 @@ void SIScheduleBlock::fastSchedule() {
}
// Returns if the register was set between first and last.
static bool isDefBetween(unsigned Reg,
SlotIndex First, SlotIndex Last,
const MachineRegisterInfo *MRI,
const LiveIntervals *LIS) {
static bool isDefBetween(Register Reg, SlotIndex First, SlotIndex Last,
const MachineRegisterInfo *MRI,
const LiveIntervals *LIS) {
for (MachineRegisterInfo::def_instr_iterator
UI = MRI->def_instr_begin(Reg),
UE = MRI->def_instr_end(); UI != UE; ++UI) {
@ -581,11 +580,11 @@ void SIScheduleBlock::printDebug(bool full) {
<< LiveOutPressure[AMDGPU::RegisterPressureSets::SReg_32] << ' '
<< LiveOutPressure[AMDGPU::RegisterPressureSets::VGPR_32] << "\n\n";
dbgs() << "LiveIns:\n";
for (unsigned Reg : LiveInRegs)
for (Register Reg : LiveInRegs)
dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
dbgs() << "\nLiveOuts:\n";
for (unsigned Reg : LiveOutRegs)
for (Register Reg : LiveOutRegs)
dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
}
@ -1413,12 +1412,12 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
// highest topological index.
LiveOutRegsNumUsages.resize(Blocks.size());
for (SIScheduleBlock *Block : Blocks) {
for (unsigned Reg : Block->getInRegs()) {
for (Register Reg : Block->getInRegs()) {
bool Found = false;
int topoInd = -1;
for (SIScheduleBlock* Pred: Block->getPreds()) {
std::set<unsigned> PredOutRegs = Pred->getOutRegs();
std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
std::set<Register> PredOutRegs = Pred->getOutRegs();
std::set<Register>::iterator RegPos = PredOutRegs.find(Reg);
if (RegPos != PredOutRegs.end()) {
Found = true;
@ -1453,18 +1452,18 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
}
#endif
std::set<unsigned> InRegs = DAG->getInRegs();
std::set<Register> InRegs = DAG->getInRegs();
addLiveRegs(InRegs);
// Increase LiveOutRegsNumUsages for blocks
// producing registers consumed in another
// scheduling region.
for (unsigned Reg : DAG->getOutRegs()) {
for (Register Reg : DAG->getOutRegs()) {
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
// Do reverse traversal
int ID = BlocksStruct.TopDownIndex2Block[Blocks.size()-1-i];
SIScheduleBlock *Block = Blocks[ID];
const std::set<unsigned> &OutRegs = Block->getOutRegs();
const std::set<Register> &OutRegs = Block->getOutRegs();
if (OutRegs.find(Reg) == OutRegs.end())
continue;
@ -1477,11 +1476,11 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
// Fill LiveRegsConsumers for regs that were already
// defined before scheduling.
for (SIScheduleBlock *Block : Blocks) {
for (unsigned Reg : Block->getInRegs()) {
for (Register Reg : Block->getInRegs()) {
bool Found = false;
for (SIScheduleBlock* Pred: Block->getPreds()) {
std::set<unsigned> PredOutRegs = Pred->getOutRegs();
std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
std::set<Register> PredOutRegs = Pred->getOutRegs();
std::set<Register>::iterator RegPos = PredOutRegs.find(Reg);
if (RegPos != PredOutRegs.end()) {
Found = true;
@ -1573,13 +1572,11 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() {
if (SregCurrentUsage > maxSregUsage)
maxSregUsage = SregCurrentUsage;
LLVM_DEBUG(dbgs() << "Picking New Blocks\n"; dbgs() << "Available: ";
for (SIScheduleBlock *Block
: ReadyBlocks) dbgs()
<< Block->getID() << ' ';
for (SIScheduleBlock *Block : ReadyBlocks)
dbgs() << Block->getID() << ' ';
dbgs() << "\nCurrent Live:\n";
for (unsigned Reg
: LiveRegs) dbgs()
<< printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
for (Register Reg : LiveRegs)
dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
dbgs() << '\n';
dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n';
dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n';);
@ -1634,7 +1631,7 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() {
// Tracking of currently alive registers to determine VGPR Usage.
void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) {
void SIScheduleBlockScheduler::addLiveRegs(std::set<Register> &Regs) {
for (Register Reg : Regs) {
// For now only track virtual registers.
if (!Reg.isVirtual())
@ -1645,10 +1642,10 @@ void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) {
}
void SIScheduleBlockScheduler::decreaseLiveRegs(SIScheduleBlock *Block,
std::set<unsigned> &Regs) {
for (unsigned Reg : Regs) {
std::set<Register> &Regs) {
for (Register Reg : Regs) {
// For now only track virtual registers.
std::set<unsigned>::iterator Pos = LiveRegs.find(Reg);
std::set<Register>::iterator Pos = LiveRegs.find(Reg);
assert (Pos != LiveRegs.end() && // Reg must be live.
LiveRegsConsumers.find(Reg) != LiveRegsConsumers.end() &&
LiveRegsConsumers[Reg] >= 1);
@ -1687,8 +1684,8 @@ void SIScheduleBlockScheduler::blockScheduled(SIScheduleBlock *Block) {
}
std::vector<int>
SIScheduleBlockScheduler::checkRegUsageImpact(std::set<unsigned> &InRegs,
std::set<unsigned> &OutRegs) {
SIScheduleBlockScheduler::checkRegUsageImpact(std::set<Register> &InRegs,
std::set<Register> &OutRegs) {
std::vector<int> DiffSetPressure;
DiffSetPressure.assign(DAG->getTRI()->getNumRegPressureSets(), 0);

26
llvm/lib/Target/AMDGPU/SIMachineScheduler.h
View File

@ -81,8 +81,8 @@ class SIScheduleBlock {
// Note that some registers are not 32 bits,
// and thus the pressure is not equal
// to the number of live registers.
std::set<unsigned> LiveInRegs;
std::set<unsigned> LiveOutRegs;
std::set<Register> LiveInRegs;
std::set<Register> LiveOutRegs;
bool Scheduled = false;
bool HighLatencyBlock = false;
@ -157,8 +157,8 @@ public:
return InternalAdditionalPressure;
}
std::set<unsigned> &getInRegs() { return LiveInRegs; }
std::set<unsigned> &getOutRegs() { return LiveOutRegs; }
std::set<Register> &getInRegs() { return LiveInRegs; }
std::set<Register> &getOutRegs() { return LiveOutRegs; }
void printDebug(bool Full);
@ -320,10 +320,10 @@ class SIScheduleBlockScheduler {
SISchedulerBlockSchedulerVariant Variant;
std::vector<SIScheduleBlock*> Blocks;
std::vector<std::map<unsigned, unsigned>> LiveOutRegsNumUsages;
std::set<unsigned> LiveRegs;
std::vector<std::map<Register, unsigned>> LiveOutRegsNumUsages;
std::set<Register> LiveRegs;
// Num of schedulable unscheduled blocks reading the register.
std::map<unsigned, unsigned> LiveRegsConsumers;
std::map<Register, unsigned> LiveRegsConsumers;
std::vector<unsigned> LastPosHighLatencyParentScheduled;
int LastPosWaitedHighLatency;
@ -389,15 +389,15 @@ private:
SIBlockSchedCandidate &TryCand);
SIScheduleBlock *pickBlock();
void addLiveRegs(std::set<unsigned> &Regs);
void decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs);
void addLiveRegs(std::set<Register> &Regs);
void decreaseLiveRegs(SIScheduleBlock *Block, std::set<Register> &Regs);
void releaseBlockSuccs(SIScheduleBlock *Parent);
void blockScheduled(SIScheduleBlock *Block);
// Check register pressure change
// by scheduling a block with these LiveIn and LiveOut.
std::vector<int> checkRegUsageImpact(std::set<unsigned> &InRegs,
std::set<unsigned> &OutRegs);
std::vector<int> checkRegUsageImpact(std::set<Register> &InRegs,
std::set<Register> &OutRegs);
void schedule();
};
@ -462,8 +462,8 @@ public:
unsigned &VgprUsage,
unsigned &SgprUsage);
std::set<unsigned> getInRegs() {
std::set<unsigned> InRegs;
std::set<Register> getInRegs() {
std::set<Register> InRegs;
for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
InRegs.insert(RegMaskPair.RegUnit);
}