[NVPTX] Add PRMT constant folding and cleanup usage of PRMT node (#148906)
This commit is contained in:
Alex MacLean
GitHub
parent
3b11aaaf94
commit
f480e1b825
@ -1048,9 +1048,12 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
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MVT::v32i32, MVT::v64i32, MVT::v128i32},
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Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// Enable custom lowering for the i128 bit operand with clusterlaunchcontrol
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i128, Custom);
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// Enable custom lowering for the following:
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// * MVT::i128 - clusterlaunchcontrol
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// * MVT::i32 - prmt
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// * MVT::Other - internal.addrspace.wrap
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, {MVT::i32, MVT::i128, MVT::Other},
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Custom);
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}
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const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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@ -2060,6 +2063,19 @@ NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getBuildVector(Node->getValueType(0), dl, Ops);
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}
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static SDValue getPRMT(SDValue A, SDValue B, SDValue Selector, SDLoc DL,
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SelectionDAG &DAG,
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unsigned Mode = NVPTX::PTXPrmtMode::NONE) {
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return DAG.getNode(NVPTXISD::PRMT, DL, MVT::i32,
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{A, B, Selector, DAG.getConstant(Mode, DL, MVT::i32)});
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}
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static SDValue getPRMT(SDValue A, SDValue B, uint64_t Selector, SDLoc DL,
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SelectionDAG &DAG,
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unsigned Mode = NVPTX::PTXPrmtMode::NONE) {
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return getPRMT(A, B, DAG.getConstant(Selector, DL, MVT::i32), DL, DAG, Mode);
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}
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SDValue NVPTXTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
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// Handle bitcasting from v2i8 without hitting the default promotion
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// strategy which goes through stack memory.
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@ -2111,15 +2127,12 @@ SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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L = DAG.getAnyExtOrTrunc(L, DL, MVT::i32);
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R = DAG.getAnyExtOrTrunc(R, DL, MVT::i32);
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}
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return DAG.getNode(
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NVPTXISD::PRMT, DL, MVT::v4i8,
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{L, R, DAG.getConstant(SelectionValue, DL, MVT::i32),
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DAG.getConstant(NVPTX::PTXPrmtMode::NONE, DL, MVT::i32)});
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return getPRMT(L, R, SelectionValue, DL, DAG);
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};
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auto PRMT__10 = GetPRMT(Op->getOperand(0), Op->getOperand(1), true, 0x3340);
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auto PRMT__32 = GetPRMT(Op->getOperand(2), Op->getOperand(3), true, 0x3340);
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auto PRMT3210 = GetPRMT(PRMT__10, PRMT__32, false, 0x5410);
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return DAG.getNode(ISD::BITCAST, DL, VT, PRMT3210);
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return DAG.getBitcast(VT, PRMT3210);
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}
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// Get value or the Nth operand as an APInt(32). Undef values treated as 0.
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@ -2176,11 +2189,14 @@ SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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SDValue Selector = DAG.getNode(ISD::OR, DL, MVT::i32,
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DAG.getZExtOrTrunc(Index, DL, MVT::i32),
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DAG.getConstant(0x7770, DL, MVT::i32));
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SDValue PRMT = DAG.getNode(
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NVPTXISD::PRMT, DL, MVT::i32,
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{DAG.getBitcast(MVT::i32, Vector), DAG.getConstant(0, DL, MVT::i32),
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Selector, DAG.getConstant(NVPTX::PTXPrmtMode::NONE, DL, MVT::i32)});
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return DAG.getAnyExtOrTrunc(PRMT, DL, Op->getValueType(0));
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SDValue PRMT = getPRMT(DAG.getBitcast(MVT::i32, Vector),
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DAG.getConstant(0, DL, MVT::i32), Selector, DL, DAG);
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SDValue Ext = DAG.getAnyExtOrTrunc(PRMT, DL, Op->getValueType(0));
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SDNodeFlags Flags;
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Flags.setNoSignedWrap(Ext.getScalarValueSizeInBits() > 8);
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Flags.setNoUnsignedWrap(Ext.getScalarValueSizeInBits() >= 8);
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Ext->setFlags(Flags);
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return Ext;
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}
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// Constant index will be matched by tablegen.
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@ -2242,9 +2258,9 @@ SDValue NVPTXTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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}
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SDLoc DL(Op);
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return DAG.getNode(NVPTXISD::PRMT, DL, MVT::v4i8, V1, V2,
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DAG.getConstant(Selector, DL, MVT::i32),
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DAG.getConstant(NVPTX::PTXPrmtMode::NONE, DL, MVT::i32));
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SDValue PRMT = getPRMT(DAG.getBitcast(MVT::i32, V1),
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DAG.getBitcast(MVT::i32, V2), Selector, DL, DAG);
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return DAG.getBitcast(Op.getValueType(), PRMT);
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}
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/// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
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/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
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@ -2729,10 +2745,46 @@ static SDValue LowerClusterLaunchControlQueryCancel(SDValue Op,
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{TryCancelResponse0, TryCancelResponse1});
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}
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static SDValue lowerPrmtIntrinsic(SDValue Op, SelectionDAG &DAG) {
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const unsigned Mode = [&]() {
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switch (Op->getConstantOperandVal(0)) {
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case Intrinsic::nvvm_prmt:
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return NVPTX::PTXPrmtMode::NONE;
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case Intrinsic::nvvm_prmt_b4e:
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return NVPTX::PTXPrmtMode::B4E;
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case Intrinsic::nvvm_prmt_ecl:
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return NVPTX::PTXPrmtMode::ECL;
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case Intrinsic::nvvm_prmt_ecr:
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return NVPTX::PTXPrmtMode::ECR;
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case Intrinsic::nvvm_prmt_f4e:
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return NVPTX::PTXPrmtMode::F4E;
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case Intrinsic::nvvm_prmt_rc16:
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return NVPTX::PTXPrmtMode::RC16;
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case Intrinsic::nvvm_prmt_rc8:
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return NVPTX::PTXPrmtMode::RC8;
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default:
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llvm_unreachable("unsupported/unhandled intrinsic");
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}
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}();
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SDLoc DL(Op);
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SDValue A = Op->getOperand(1);
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SDValue B = Op.getNumOperands() == 4 ? Op.getOperand(2)
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: DAG.getConstant(0, DL, MVT::i32);
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SDValue Selector = (Op->op_end() - 1)->get();
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return getPRMT(A, B, Selector, DL, DAG, Mode);
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}
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static SDValue lowerIntrinsicWOChain(SDValue Op, SelectionDAG &DAG) {
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switch (Op->getConstantOperandVal(0)) {
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default:
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return Op;
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case Intrinsic::nvvm_prmt:
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case Intrinsic::nvvm_prmt_b4e:
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case Intrinsic::nvvm_prmt_ecl:
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case Intrinsic::nvvm_prmt_ecr:
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case Intrinsic::nvvm_prmt_f4e:
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case Intrinsic::nvvm_prmt_rc16:
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case Intrinsic::nvvm_prmt_rc8:
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return lowerPrmtIntrinsic(Op, DAG);
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case Intrinsic::nvvm_internal_addrspace_wrap:
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return Op.getOperand(1);
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case Intrinsic::nvvm_clusterlaunchcontrol_query_cancel_is_canceled:
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@ -5775,11 +5827,10 @@ PerformBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
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SDLoc DL(N);
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auto &DAG = DCI.DAG;
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auto PRMT = DAG.getNode(
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NVPTXISD::PRMT, DL, MVT::v4i8,
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{Op0, Op1, DAG.getConstant((Op1Bytes << 8) | Op0Bytes, DL, MVT::i32),
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DAG.getConstant(NVPTX::PTXPrmtMode::NONE, DL, MVT::i32)});
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return DAG.getNode(ISD::BITCAST, DL, VT, PRMT);
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auto PRMT =
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getPRMT(DAG.getBitcast(MVT::i32, Op0), DAG.getBitcast(MVT::i32, Op1),
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(Op1Bytes << 8) | Op0Bytes, DL, DAG);
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return DAG.getBitcast(VT, PRMT);
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}
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static SDValue combineADDRSPACECAST(SDNode *N,
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@ -5797,47 +5848,120 @@ static SDValue combineADDRSPACECAST(SDNode *N,
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return SDValue();
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}
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// Given a constant selector value and a prmt mode, return the selector value
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// normalized to the generic prmt mode. See the PTX ISA documentation for more
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// details:
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-prmt
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static APInt getPRMTSelector(const APInt &Selector, unsigned Mode) {
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if (Mode == NVPTX::PTXPrmtMode::NONE)
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return Selector;
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const unsigned V = Selector.trunc(2).getZExtValue();
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const auto GetSelector = [](unsigned S0, unsigned S1, unsigned S2,
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unsigned S3) {
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return APInt(32, S0 | (S1 << 4) | (S2 << 8) | (S3 << 12));
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};
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switch (Mode) {
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case NVPTX::PTXPrmtMode::F4E:
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return GetSelector(V, V + 1, V + 2, V + 3);
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case NVPTX::PTXPrmtMode::B4E:
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return GetSelector(V, (V - 1) & 7, (V - 2) & 7, (V - 3) & 7);
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case NVPTX::PTXPrmtMode::RC8:
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return GetSelector(V, V, V, V);
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case NVPTX::PTXPrmtMode::ECL:
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return GetSelector(V, std::max(V, 1U), std::max(V, 2U), 3U);
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case NVPTX::PTXPrmtMode::ECR:
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return GetSelector(0, std::min(V, 1U), std::min(V, 2U), V);
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case NVPTX::PTXPrmtMode::RC16: {
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unsigned V1 = (V & 1) << 1;
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return GetSelector(V1, V1 + 1, V1, V1 + 1);
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}
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default:
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llvm_unreachable("Invalid PRMT mode");
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}
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}
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static APInt computePRMT(APInt A, APInt B, APInt Selector, unsigned Mode) {
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// {b, a} = {{b7, b6, b5, b4}, {b3, b2, b1, b0}}
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APInt BitField = B.concat(A);
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APInt SelectorVal = getPRMTSelector(Selector, Mode);
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APInt Result(32, 0);
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for (unsigned I : llvm::seq(4U)) {
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APInt Sel = SelectorVal.extractBits(4, I * 4);
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unsigned Idx = Sel.getLoBits(3).getZExtValue();
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unsigned Sign = Sel.getHiBits(1).getZExtValue();
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APInt Byte = BitField.extractBits(8, Idx * 8);
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if (Sign)
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Byte = Byte.ashr(8);
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Result.insertBits(Byte, I * 8);
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}
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return Result;
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}
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static SDValue combinePRMT(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
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CodeGenOptLevel OptLevel) {
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if (OptLevel == CodeGenOptLevel::None)
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return SDValue();
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// Constant fold PRMT
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if (isa<ConstantSDNode>(N->getOperand(0)) &&
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isa<ConstantSDNode>(N->getOperand(1)) &&
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isa<ConstantSDNode>(N->getOperand(2)))
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return DCI.DAG.getConstant(computePRMT(N->getConstantOperandAPInt(0),
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N->getConstantOperandAPInt(1),
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N->getConstantOperandAPInt(2),
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N->getConstantOperandVal(3)),
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SDLoc(N), N->getValueType(0));
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return SDValue();
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}
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SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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CodeGenOptLevel OptLevel = getTargetMachine().getOptLevel();
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switch (N->getOpcode()) {
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default: break;
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case ISD::ADD:
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return PerformADDCombine(N, DCI, OptLevel);
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case ISD::FADD:
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return PerformFADDCombine(N, DCI, OptLevel);
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case ISD::MUL:
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return PerformMULCombine(N, DCI, OptLevel);
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case ISD::SHL:
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return PerformSHLCombine(N, DCI, OptLevel);
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case ISD::AND:
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return PerformANDCombine(N, DCI);
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case ISD::UREM:
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case ISD::SREM:
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return PerformREMCombine(N, DCI, OptLevel);
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case ISD::SETCC:
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return PerformSETCCCombine(N, DCI, STI.getSmVersion());
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case ISD::LOAD:
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case NVPTXISD::LoadParamV2:
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case NVPTXISD::LoadV2:
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case NVPTXISD::LoadV4:
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return combineUnpackingMovIntoLoad(N, DCI);
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case NVPTXISD::StoreParam:
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case NVPTXISD::StoreParamV2:
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case NVPTXISD::StoreParamV4:
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return PerformStoreParamCombine(N, DCI);
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case ISD::STORE:
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case NVPTXISD::StoreV2:
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case NVPTXISD::StoreV4:
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return PerformStoreCombine(N, DCI);
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case ISD::EXTRACT_VECTOR_ELT:
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return PerformEXTRACTCombine(N, DCI);
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case ISD::VSELECT:
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return PerformVSELECTCombine(N, DCI);
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case ISD::BUILD_VECTOR:
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return PerformBUILD_VECTORCombine(N, DCI);
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case ISD::ADDRSPACECAST:
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return combineADDRSPACECAST(N, DCI);
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default:
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break;
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case ISD::ADD:
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return PerformADDCombine(N, DCI, OptLevel);
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case ISD::ADDRSPACECAST:
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return combineADDRSPACECAST(N, DCI);
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case ISD::AND:
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return PerformANDCombine(N, DCI);
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case ISD::BUILD_VECTOR:
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return PerformBUILD_VECTORCombine(N, DCI);
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case ISD::EXTRACT_VECTOR_ELT:
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return PerformEXTRACTCombine(N, DCI);
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case ISD::FADD:
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return PerformFADDCombine(N, DCI, OptLevel);
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case ISD::LOAD:
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case NVPTXISD::LoadParamV2:
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case NVPTXISD::LoadV2:
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case NVPTXISD::LoadV4:
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return combineUnpackingMovIntoLoad(N, DCI);
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case ISD::MUL:
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return PerformMULCombine(N, DCI, OptLevel);
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case NVPTXISD::PRMT:
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return combinePRMT(N, DCI, OptLevel);
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case ISD::SETCC:
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return PerformSETCCCombine(N, DCI, STI.getSmVersion());
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case ISD::SHL:
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return PerformSHLCombine(N, DCI, OptLevel);
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case ISD::SREM:
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case ISD::UREM:
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return PerformREMCombine(N, DCI, OptLevel);
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case NVPTXISD::StoreParam:
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case NVPTXISD::StoreParamV2:
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case NVPTXISD::StoreParamV4:
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return PerformStoreParamCombine(N, DCI);
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case ISD::STORE:
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case NVPTXISD::StoreV2:
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case NVPTXISD::StoreV4:
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return PerformStoreCombine(N, DCI);
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case ISD::VSELECT:
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return PerformVSELECTCombine(N, DCI);
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}
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return SDValue();
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}
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@ -6387,7 +6511,7 @@ static void computeKnownBitsForPRMT(const SDValue Op, KnownBits &Known,
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ConstantSDNode *Selector = dyn_cast<ConstantSDNode>(Op.getOperand(2));
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unsigned Mode = Op.getConstantOperandVal(3);
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if (Mode != NVPTX::PTXPrmtMode::NONE || !Selector)
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if (!Selector)
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return;
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KnownBits AKnown = DAG.computeKnownBits(A, Depth);
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@ -6396,7 +6520,7 @@ static void computeKnownBitsForPRMT(const SDValue Op, KnownBits &Known,
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// {b, a} = {{b7, b6, b5, b4}, {b3, b2, b1, b0}}
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KnownBits BitField = BKnown.concat(AKnown);
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APInt SelectorVal = Selector->getAPIntValue();
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APInt SelectorVal = getPRMTSelector(Selector->getAPIntValue(), Mode);
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for (unsigned I : llvm::seq(std::min(4U, Known.getBitWidth() / 8))) {
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APInt Sel = SelectorVal.extractBits(4, I * 4);
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unsigned Idx = Sel.getLoBits(3).getZExtValue();
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@ -1453,18 +1453,33 @@ let hasSideEffects = false in {
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(ins PrmtMode:$mode),
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"prmt.b32$mode",
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[(set i32:$d, (prmt i32:$a, i32:$b, imm:$c, imm:$mode))]>;
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def PRMT_B32rir
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: BasicFlagsNVPTXInst<(outs B32:$d),
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(ins B32:$a, i32imm:$b, B32:$c),
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(ins PrmtMode:$mode),
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"prmt.b32$mode",
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[(set i32:$d, (prmt i32:$a, imm:$b, i32:$c, imm:$mode))]>;
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def PRMT_B32rii
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: BasicFlagsNVPTXInst<(outs B32:$d),
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(ins B32:$a, i32imm:$b, Hexu32imm:$c),
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(ins PrmtMode:$mode),
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"prmt.b32$mode",
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[(set i32:$d, (prmt i32:$a, imm:$b, imm:$c, imm:$mode))]>;
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def PRMT_B32rir
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def PRMT_B32irr
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: BasicFlagsNVPTXInst<(outs B32:$d),
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(ins B32:$a, i32imm:$b, B32:$c),
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(ins PrmtMode:$mode),
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(ins i32imm:$a, B32:$b, B32:$c), (ins PrmtMode:$mode),
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"prmt.b32$mode",
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[(set i32:$d, (prmt i32:$a, imm:$b, i32:$c, imm:$mode))]>;
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[(set i32:$d, (prmt imm:$a, i32:$b, i32:$c, imm:$mode))]>;
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def PRMT_B32iri
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: BasicFlagsNVPTXInst<(outs B32:$d),
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(ins i32imm:$a, B32:$b, Hexu32imm:$c), (ins PrmtMode:$mode),
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"prmt.b32$mode",
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[(set i32:$d, (prmt imm:$a, i32:$b, imm:$c, imm:$mode))]>;
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def PRMT_B32iir
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: BasicFlagsNVPTXInst<(outs B32:$d),
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(ins i32imm:$a, i32imm:$b, B32:$c), (ins PrmtMode:$mode),
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"prmt.b32$mode",
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[(set i32:$d, (prmt imm:$a, imm:$b, i32:$c, imm:$mode))]>;
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}
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@ -1047,24 +1047,6 @@ class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
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// MISC
|
||||
//
|
||||
|
||||
class PRMT3Pat<Intrinsic prmt_intrinsic, PatLeaf prmt_mode>
|
||||
: Pat<(prmt_intrinsic i32:$a, i32:$b, i32:$c),
|
||||
(PRMT_B32rrr $a, $b, $c, prmt_mode)>;
|
||||
|
||||
class PRMT2Pat<Intrinsic prmt_intrinsic, PatLeaf prmt_mode>
|
||||
: Pat<(prmt_intrinsic i32:$a, i32:$c),
|
||||
(PRMT_B32rir $a, (i32 0), $c, prmt_mode)>;
|
||||
|
||||
def : PRMT3Pat<int_nvvm_prmt, PrmtNONE>;
|
||||
def : PRMT3Pat<int_nvvm_prmt_f4e, PrmtF4E>;
|
||||
def : PRMT3Pat<int_nvvm_prmt_b4e, PrmtB4E>;
|
||||
|
||||
def : PRMT2Pat<int_nvvm_prmt_rc8, PrmtRC8>;
|
||||
def : PRMT2Pat<int_nvvm_prmt_ecl, PrmtECL>;
|
||||
def : PRMT2Pat<int_nvvm_prmt_ecr, PrmtECR>;
|
||||
def : PRMT2Pat<int_nvvm_prmt_rc16, PrmtRC16>;
|
||||
|
||||
|
||||
def INT_NVVM_NANOSLEEP_I : BasicNVPTXInst<(outs), (ins i32imm:$i), "nanosleep.u32",
|
||||
[(int_nvvm_nanosleep imm:$i)]>,
|
||||
Requires<[hasPTX<63>, hasSM<70>]>;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
171
llvm/test/CodeGen/NVPTX/prmt-const-folding.ll
Normal file
171
llvm/test/CodeGen/NVPTX/prmt-const-folding.ll
Normal file
@ -0,0 +1,171 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc < %s -verify-machineinstrs -mcpu=sm_50 | FileCheck %s
|
||||
; RUN: %if ptxas %{ llc < %s -verify-machineinstrs -mcpu=sm_50 | %ptxas-verify %}
|
||||
|
||||
target triple = "nvptx64-nvidia-cuda"
|
||||
|
||||
@g = global i32 0
|
||||
|
||||
define void @test_prmt_f4e() {
|
||||
; CHECK-LABEL: test_prmt_f4e(
|
||||
; CHECK: {
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: // %bb.0:
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50462976;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 67305985;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 84148994;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 100992003;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50462976;
|
||||
; CHECK-NEXT: ret;
|
||||
%v1 = call i32 @llvm.nvvm.prmt.f4e(i32 u0x03020100, i32 u0x07060504, i32 u0x0)
|
||||
store volatile i32 %v1, ptr @g
|
||||
%v2 = call i32 @llvm.nvvm.prmt.f4e(i32 u0x03020100, i32 u0x07060504, i32 u0x1)
|
||||
store volatile i32 %v2, ptr @g
|
||||
%v3 = call i32 @llvm.nvvm.prmt.f4e(i32 u0x03020100, i32 u0x07060504, i32 u0x2)
|
||||
store volatile i32 %v3, ptr @g
|
||||
%v4 = call i32 @llvm.nvvm.prmt.f4e(i32 u0x03020100, i32 u0x07060504, i32 u0x3)
|
||||
store volatile i32 %v4, ptr @g
|
||||
%v5 = call i32 @llvm.nvvm.prmt.f4e(i32 u0x03020100, i32 u0x07060504, i32 u0x4)
|
||||
store volatile i32 %v5, ptr @g
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_prmt_b4e() {
|
||||
; CHECK-LABEL: test_prmt_b4e(
|
||||
; CHECK: {
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: // %bb.0:
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 84281088;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 101122049;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 117440770;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 66051;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 84281088;
|
||||
; CHECK-NEXT: ret;
|
||||
%v1 = call i32 @llvm.nvvm.prmt.b4e(i32 u0x03020100, i32 u0x07060504, i32 u0x0)
|
||||
store volatile i32 %v1, ptr @g
|
||||
%v2 = call i32 @llvm.nvvm.prmt.b4e(i32 u0x03020100, i32 u0x07060504, i32 u0x1)
|
||||
store volatile i32 %v2, ptr @g
|
||||
%v3 = call i32 @llvm.nvvm.prmt.b4e(i32 u0x03020100, i32 u0x07060504, i32 u0x2)
|
||||
store volatile i32 %v3, ptr @g
|
||||
%v4 = call i32 @llvm.nvvm.prmt.b4e(i32 u0x03020100, i32 u0x07060504, i32 u0x3)
|
||||
store volatile i32 %v4, ptr @g
|
||||
%v5 = call i32 @llvm.nvvm.prmt.b4e(i32 u0x03020100, i32 u0x07060504, i32 u0x4)
|
||||
store volatile i32 %v5, ptr @g
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_prmt_ecl() {
|
||||
; CHECK-LABEL: test_prmt_ecl(
|
||||
; CHECK: {
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: // %bb.0:
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50462976;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50462977;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50463234;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50529027;
|
||||
; CHECK-NEXT: ret;
|
||||
%v1 = call i32 @llvm.nvvm.prmt.ecl(i32 u0x03020100, i32 u0x0)
|
||||
store volatile i32 %v1, ptr @g
|
||||
%v2 = call i32 @llvm.nvvm.prmt.ecl(i32 u0x03020100, i32 u0x1)
|
||||
store volatile i32 %v2, ptr @g
|
||||
%v3 = call i32 @llvm.nvvm.prmt.ecl(i32 u0x03020100, i32 u0x2)
|
||||
store volatile i32 %v3, ptr @g
|
||||
%v4 = call i32 @llvm.nvvm.prmt.ecl(i32 u0x03020100, i32 u0x3)
|
||||
store volatile i32 %v4, ptr @g
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_prmt_ecr() {
|
||||
; CHECK-LABEL: test_prmt_ecr(
|
||||
; CHECK: {
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: // %bb.0:
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 0;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 16843008;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 33685760;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50462976;
|
||||
; CHECK-NEXT: ret;
|
||||
%v1 = call i32 @llvm.nvvm.prmt.ecr(i32 u0x03020100, i32 u0x0)
|
||||
store volatile i32 %v1, ptr @g
|
||||
%v2 = call i32 @llvm.nvvm.prmt.ecr(i32 u0x03020100, i32 u0x1)
|
||||
store volatile i32 %v2, ptr @g
|
||||
%v3 = call i32 @llvm.nvvm.prmt.ecr(i32 u0x03020100, i32 u0x2)
|
||||
store volatile i32 %v3, ptr @g
|
||||
%v4 = call i32 @llvm.nvvm.prmt.ecr(i32 u0x03020100, i32 u0x3)
|
||||
store volatile i32 %v4, ptr @g
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_prmt_rc8() {
|
||||
; CHECK-LABEL: test_prmt_rc8(
|
||||
; CHECK: {
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: // %bb.0:
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 0;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 16843009;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 33686018;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50529027;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 0;
|
||||
; CHECK-NEXT: ret;
|
||||
%v1 = call i32 @llvm.nvvm.prmt.rc8(i32 u0x03020100, i32 u0x0)
|
||||
store volatile i32 %v1, ptr @g
|
||||
%v2 = call i32 @llvm.nvvm.prmt.rc8(i32 u0x03020100, i32 u0x1)
|
||||
store volatile i32 %v2, ptr @g
|
||||
%v3 = call i32 @llvm.nvvm.prmt.rc8(i32 u0x03020100, i32 u0x2)
|
||||
store volatile i32 %v3, ptr @g
|
||||
%v4 = call i32 @llvm.nvvm.prmt.rc8(i32 u0x03020100, i32 u0x3)
|
||||
store volatile i32 %v4, ptr @g
|
||||
%v5 = call i32 @llvm.nvvm.prmt.rc8(i32 u0x03020100, i32 u0x4)
|
||||
store volatile i32 %v5, ptr @g
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_prmt_rc16() {
|
||||
; CHECK-LABEL: test_prmt_rc16(
|
||||
; CHECK: {
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: // %bb.0:
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 16777472;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 50463490;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 16777472;
|
||||
; CHECK-NEXT: ret;
|
||||
%v1 = call i32 @llvm.nvvm.prmt.rc16(i32 u0x03020100, i32 u0x0)
|
||||
store volatile i32 %v1, ptr @g
|
||||
%v2 = call i32 @llvm.nvvm.prmt.rc16(i32 u0x03020100, i32 u0x1)
|
||||
store volatile i32 %v2, ptr @g
|
||||
%v3 = call i32 @llvm.nvvm.prmt.rc16(i32 u0x03020100, i32 u0x2)
|
||||
store volatile i32 %v3, ptr @g
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define void @test_prmt_basic() {
|
||||
; CHECK-LABEL: test_prmt_basic(
|
||||
; CHECK: {
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: // %bb.0:
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 66051;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 117507841;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 1146447479;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], 0;
|
||||
; CHECK-NEXT: st.volatile.global.b32 [g], -16711936;
|
||||
; CHECK-NEXT: ret;
|
||||
%v1 = call i32 @llvm.nvvm.prmt(i32 u0x03020100, i32 u0x07060504, i32 u0x0123)
|
||||
store volatile i32 %v1, ptr @g
|
||||
%v2 = call i32 @llvm.nvvm.prmt(i32 u0x03020100, i32 u0x07060504, i32 u0x7171)
|
||||
store volatile i32 %v2, ptr @g
|
||||
%v3 = call i32 @llvm.nvvm.prmt(i32 u0x33221100, i32 u0x77665544, i32 u0x4567)
|
||||
store volatile i32 %v3, ptr @g
|
||||
%v4 = call i32 @llvm.nvvm.prmt(i32 u0x33221100, i32 u0x77665544, i32 u0xBA98)
|
||||
store volatile i32 %v4, ptr @g
|
||||
%v5 = call i32 @llvm.nvvm.prmt(i32 u0xF322F100, i32 u0x77665544, i32 u0xBA98)
|
||||
store volatile i32 %v5, ptr @g
|
||||
ret void
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user