[lldb] AArch64 register 33 is not cpsr (#183860)
I have an unwind failure where the eh_frame for a trap handler states that the caller's return address is in eh_frame register 33, which lldb treats as cpsr. https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#dwarf-register-names Register 33 is ELR_mode, which isn't defined as a register in any of the AArch64 register definition files in lldb today, so I'm not adding it to the header files. rdar://170602999
This commit is contained in:
Jason Molenda
GitHub
parent
685a65a7f0
commit
f4e64ceb4b
@ -71,8 +71,6 @@ std::pair<uint32_t, uint32_t>
|
||||
ABIAArch64::GetEHAndDWARFNums(llvm::StringRef name) {
|
||||
if (name == "pc")
|
||||
return {arm64_ehframe::pc, arm64_dwarf::pc};
|
||||
if (name == "cpsr")
|
||||
return {arm64_ehframe::cpsr, arm64_dwarf::cpsr};
|
||||
return MCBasedABI::GetEHAndDWARFNums(name);
|
||||
}
|
||||
|
||||
|
||||
@ -768,8 +768,6 @@ uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber(
|
||||
return gpr_lr;
|
||||
case arm64_dwarf::pc:
|
||||
return gpr_pc;
|
||||
case arm64_dwarf::cpsr:
|
||||
return gpr_cpsr;
|
||||
|
||||
case arm64_dwarf::v0:
|
||||
return fpu_v0;
|
||||
@ -907,8 +905,6 @@ uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber(
|
||||
return gpr_lr;
|
||||
case arm64_ehframe::pc:
|
||||
return gpr_pc;
|
||||
case arm64_ehframe::cpsr:
|
||||
return gpr_cpsr;
|
||||
}
|
||||
} else if (kind == eRegisterKindLLDB) {
|
||||
return reg;
|
||||
|
||||
@ -486,9 +486,6 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
|
||||
// Generates register kinds array for vector registers
|
||||
#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
|
||||
#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
|
||||
#define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, LLDB_REGNUM_GENERIC_FLAGS)
|
||||
#define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
|
||||
#define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
|
||||
|
||||
// Defines a 64-bit general purpose register
|
||||
#define DEFINE_GPR64(reg, generic_kind) \
|
||||
@ -538,6 +535,15 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
|
||||
nullptr, \
|
||||
}
|
||||
|
||||
// Defines miscellaneous status and control registers like cpsr, fpsr etc
|
||||
// that have no DWARF/eh_frame register numbers.
|
||||
#define DEFINE_MISC_LLDB_REGS(reg, size, TYPE, lldb_kind) \
|
||||
{ \
|
||||
#reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint, \
|
||||
lldb::eFormatHex, LLDB_KIND(lldb_kind), nullptr, nullptr, \
|
||||
nullptr, \
|
||||
}
|
||||
|
||||
// Defines pointer authentication mask registers
|
||||
#define DEFINE_EXTENSION_REG(reg) \
|
||||
{ \
|
||||
@ -588,8 +594,8 @@ static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
|
||||
DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
|
||||
DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
|
||||
|
||||
// DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
|
||||
// DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_LLDB_REGS(cpsr, 4, GPR, gpr_cpsr),
|
||||
|
||||
// DEFINE_GPR32(name, parent name)
|
||||
DEFINE_GPR32(w0, x0),
|
||||
@ -723,12 +729,12 @@ static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
|
||||
DEFINE_FPU_PSEUDO(d30, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v30),
|
||||
DEFINE_FPU_PSEUDO(d31, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v31),
|
||||
|
||||
// DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
|
||||
DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
|
||||
DEFINE_MISC_REGS(far, 8, EXC, exc_far),
|
||||
DEFINE_MISC_REGS(esr, 4, EXC, exc_esr),
|
||||
DEFINE_MISC_REGS(exception, 4, EXC, exc_exception),
|
||||
// DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_LLDB_REGS(fpsr, 4, FPU, fpu_fpsr),
|
||||
DEFINE_MISC_LLDB_REGS(fpcr, 4, FPU, fpu_fpcr),
|
||||
DEFINE_MISC_LLDB_REGS(far, 8, EXC, exc_far),
|
||||
DEFINE_MISC_LLDB_REGS(esr, 4, EXC, exc_esr),
|
||||
DEFINE_MISC_LLDB_REGS(exception, 4, EXC, exc_exception),
|
||||
|
||||
{DEFINE_DBG(bvr, 0)},
|
||||
{DEFINE_DBG(bvr, 1)},
|
||||
|
||||
@ -373,8 +373,8 @@ static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
|
||||
DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
|
||||
DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
|
||||
|
||||
// DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
|
||||
// DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_LLDB_REGS(cpsr, 4, GPR, gpr_cpsr),
|
||||
|
||||
// DEFINE_GPR32(name, parent name)
|
||||
DEFINE_GPR32(w0, x0),
|
||||
@ -508,9 +508,9 @@ static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
|
||||
DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
|
||||
DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
|
||||
|
||||
// DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
|
||||
DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
|
||||
// DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
|
||||
DEFINE_MISC_LLDB_REGS(fpsr, 4, FPU, fpu_fpsr),
|
||||
DEFINE_MISC_LLDB_REGS(fpcr, 4, FPU, fpu_fpcr),
|
||||
|
||||
DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
|
||||
// DEFINE_ZREG(name)
|
||||
|
||||
@ -398,7 +398,7 @@ static RegisterInfo g_reg_infos[] = {
|
||||
OFFSET(cpsr),
|
||||
eEncodingUint,
|
||||
eFormatHex,
|
||||
{INV, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, INV, reg_cpsr},
|
||||
{INV, INV, LLDB_REGNUM_GENERIC_FLAGS, INV, reg_cpsr},
|
||||
nullptr,
|
||||
nullptr,
|
||||
nullptr,
|
||||
|
||||
@ -50,8 +50,14 @@ enum {
|
||||
x31 = 31,
|
||||
sp = x31,
|
||||
pc = 32,
|
||||
cpsr = 33,
|
||||
// 34-45 reserved
|
||||
elr_mode = 33,
|
||||
ra_sign_state = 34,
|
||||
tpidrr0_el0 = 35,
|
||||
tpidr_el0 = 36,
|
||||
tpidr_el1 = 37,
|
||||
tpidr_el2 = 38,
|
||||
tpidr_el3 = 39,
|
||||
// 40-45 Reserved
|
||||
|
||||
// 64-bit SVE Vector granule pseudo register
|
||||
vg = 46,
|
||||
|
||||
@ -49,8 +49,14 @@ enum {
|
||||
lr, // aka x30
|
||||
sp, // aka x31 aka wzr
|
||||
pc, // value is 32
|
||||
cpsr,
|
||||
// 34-45 reserved
|
||||
elr_mode = 33,
|
||||
ra_sign_state = 34,
|
||||
tpidrr0_el0 = 35,
|
||||
tpidr_el0 = 36,
|
||||
tpidr_el1 = 37,
|
||||
tpidr_el2 = 38,
|
||||
tpidr_el3 = 39,
|
||||
// 40-45 Reserved
|
||||
|
||||
// 64-bit SVE Vector granule pseudo register
|
||||
vg = 46,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user