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Revert "Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (#144402)"

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Since the fix https://github.com/llvm/llvm-project/pull/144848 for post-commit CI failure
has landed.

This reverts commit f83d09a1f60aee28a8ed9020cd72971ec2885f24.
This commit is contained in:
Jim Lin 2025-06-22 17:52:30 +08:00
parent 8583882bdc
commit f78819aeef
8 changed files with 7 additions and 41 deletions
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7
clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
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@ -10,7 +10,6 @@
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@ -19,12 +18,8 @@
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0

6
clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
View File

@ -10,7 +10,6 @@
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@ -19,11 +18,8 @@
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0

7
clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
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@ -10,7 +10,6 @@
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@ -18,12 +17,8 @@
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0

6
clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
View File

@ -10,7 +10,6 @@
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@ -18,11 +17,8 @@
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0

6
clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
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@ -10,7 +10,6 @@
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@ -19,11 +18,8 @@
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0

6
clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c
View File

@ -10,7 +10,6 @@
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@ -18,11 +17,8 @@
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0

8
llvm/lib/Target/RISCV/RISCVProcessors.td
View File

@ -703,8 +703,6 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureStdExtZbc,
FeatureVendorXAndesPerf]>;
def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
@ -718,8 +716,6 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureStdExtZbc,
FeatureVendorXAndesPerf]>;
defvar Andes45TuneFeatures = [TuneAndes45,
@ -741,7 +737,6 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureVendorXAndesPerf],
Andes45TuneFeatures>;
@ -756,7 +751,6 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureVendorXAndesPerf],
Andes45TuneFeatures>;
@ -771,7 +765,6 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureVendorXAndesPerf],
Andes45TuneFeatures>;
@ -786,6 +779,5 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureVendorXAndesPerf],
Andes45TuneFeatures>;

2
llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
View File

@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+zbc -timeline -iterations=1 < %s | FileCheck %s
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s
# Two ALUs without dependency can be dispatched in the same cycle.
add a0, a0, a0