[SPIR-V] Add SPV_INTEL_predicated_io extension (#161591)
This PR introduces the support for the SPIR-V extension `SPV_INTEL_predicated_io`. This extension adds predicated load and store instructions. Predicated load performs load from memory if predicate is true; otherwise, it uses default_value as a result. Predicated store performs store of value to memory if predicate is true; otherwise, it does nothing. Reference Specification: https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_predicated_io.asciidoc
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YixingZhang007
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@ -233,6 +233,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
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- Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
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* - ``SPV_KHR_float_controls2``
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- Adds execution modes and decorations to control floating-point computations in both kernels and shaders. It can be used on whole modules and individual instructions.
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* - ``SPV_INTEL_predicated_io``
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- Adds predicated load and store instructions that conditionally read from or write to memory based on a boolean predicate.
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SPIR-V representation in LLVM IR
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================================
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@ -284,6 +284,17 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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}
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break;
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}
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case SPIRV::OpPredicatedLoadINTEL:
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case SPIRV::OpPredicatedStoreINTEL: {
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const unsigned NumOps = MI->getNumOperands();
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if (NumOps > NumFixedOps) {
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OS << ' ';
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printSymbolicOperand<OperandCategory::MemoryOperandOperand>(
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MI, NumOps - 1, OS);
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break;
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}
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break;
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}
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default:
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printRemainingVariableOps(MI, NumFixedOps, OS);
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break;
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@ -2419,6 +2419,27 @@ static bool generatePipeInst(const SPIRV::IncomingCall *Call,
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return buildPipeInst(Call, Opcode, Scope, MIRBuilder, GR);
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}
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static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
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MachineIRBuilder &MIRBuilder,
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SPIRVGlobalRegistry *GR) {
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const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
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unsigned Opcode =
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SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
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bool IsSet = Opcode != SPIRV::OpPredicatedStoreINTEL;
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unsigned ArgSz = Call->Arguments.size();
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SmallVector<uint32_t, 1> ImmArgs;
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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// Memory operand is optional and is literal.
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if (ArgSz > 3)
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ImmArgs.push_back(
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getConstFromIntrinsic(Call->Arguments[/*Literal index*/ 3], MRI));
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Register TypeReg = GR->getSPIRVTypeID(Call->ReturnType);
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return buildOpFromWrapper(MIRBuilder, Opcode, Call,
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IsSet ? TypeReg : Register(0), ImmArgs);
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}
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static bool buildNDRange(const SPIRV::IncomingCall *Call,
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MachineIRBuilder &MIRBuilder,
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SPIRVGlobalRegistry *GR) {
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@ -3019,6 +3040,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
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return generate2DBlockIOINTELInst(Call.get(), MIRBuilder, GR);
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case SPIRV::Pipe:
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return generatePipeInst(Call.get(), MIRBuilder, GR);
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case SPIRV::PredicatedLoadStore:
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return generatePredicatedLoadStoreInst(Call.get(), MIRBuilder, GR);
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}
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return false;
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}
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@ -70,6 +70,7 @@ def BindlessINTEL : BuiltinGroup;
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def TernaryBitwiseINTEL : BuiltinGroup;
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def Block2DLoadStore : BuiltinGroup;
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def Pipe : BuiltinGroup;
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def PredicatedLoadStore : BuiltinGroup;
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//===----------------------------------------------------------------------===//
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// Class defining a demangled builtin record. The information in the record
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@ -752,6 +753,10 @@ defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadTransformINTEL", OpenC
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defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockPrefetchINTEL", OpenCL_std, Block2DLoadStore, 9, 9, OpSubgroup2DBlockPrefetchINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockStoreINTEL", OpenCL_std, Block2DLoadStore, 10, 10, OpSubgroup2DBlockStoreINTEL>;
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// SPV_INTEL_predicated_io builtin records
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defm : DemangledNativeBuiltin<"__spirv_PredicatedLoadINTEL", OpenCL_std, PredicatedLoadStore, 3, 4, OpPredicatedLoadINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_PredicatedStoreINTEL", OpenCL_std, PredicatedLoadStore, 3, 4, OpPredicatedStoreINTEL>;
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//===----------------------------------------------------------------------===//
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// Class defining a work/sub group builtin that should be translated into a
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// SPIR-V instruction using the defined properties.
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@ -151,7 +151,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
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{"SPV_KHR_bfloat16", SPIRV::Extension::Extension::SPV_KHR_bfloat16},
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{"SPV_EXT_relaxed_printf_string_address_space",
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SPIRV::Extension::Extension::
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SPV_EXT_relaxed_printf_string_address_space}};
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SPV_EXT_relaxed_printf_string_address_space},
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{"SPV_INTEL_predicated_io",
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SPIRV::Extension::Extension::SPV_INTEL_predicated_io}};
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bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
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StringRef ArgValue,
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@ -987,3 +987,9 @@ def OpSubgroup2DBlockPrefetchINTEL: Op<6234, (outs), (ins ID:$element_size, ID:$
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def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
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ID:$block_count, ID:$src_ptr, ID:$dst_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord),
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"OpSubgroup2DBlockStoreINTEL $element_size $block_width $block_height $block_count $src_ptr $dst_base_ptr $memory_width $memory_height $memory_pitch $coord">;
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// SPV_INTEL_predicated_io
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def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr, ID:$predicate, ID:$default_value, variable_ops),
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"$res = OpPredicatedLoadINTEL $resType $ptr $predicate $default_value">;
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def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
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"OpPredicatedStoreINTEL $ptr $object $predicate">;
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@ -2035,6 +2035,17 @@ void addInstrRequirements(const MachineInstr &MI,
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// TODO: Add UntypedPointersKHR when implemented.
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break;
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}
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case SPIRV::OpPredicatedLoadINTEL:
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case SPIRV::OpPredicatedStoreINTEL: {
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if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_predicated_io))
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report_fatal_error(
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"OpPredicated[Load/Store]INTEL instructions require "
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"the following SPIR-V extension: SPV_INTEL_predicated_io",
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false);
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Reqs.addExtension(SPIRV::Extension::SPV_INTEL_predicated_io);
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Reqs.addCapability(SPIRV::Capability::PredicatedIOINTEL);
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break;
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}
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default:
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break;
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@ -385,6 +385,7 @@ defm SPV_INTEL_int4 : ExtensionOperand<123, [EnvOpenCL]>;
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defm SPV_KHR_float_controls2 : ExtensionOperand<124, [EnvVulkan, EnvOpenCL]>;
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defm SPV_INTEL_tensor_float32_conversion : ExtensionOperand<125, [EnvOpenCL]>;
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defm SPV_KHR_bfloat16 : ExtensionOperand<126, [EnvVulkan, EnvOpenCL]>;
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defm SPV_INTEL_predicated_io : ExtensionOperand<127, [EnvOpenCL]>;
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//===----------------------------------------------------------------------===//
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// Multiclass used to define Capabilities enum values and at the same time
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@ -594,6 +595,7 @@ defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_
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defm Subgroup2DBlockIOINTEL : CapabilityOperand<6228, 0, 0, [SPV_INTEL_2d_block_io], []>;
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defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
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defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
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defm PredicatedIOINTEL : CapabilityOperand<6257, 0, 0, [SPV_INTEL_predicated_io], []>;
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defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
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defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
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defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>;
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@ -0,0 +1,36 @@
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; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
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; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_predicated_io %s -o - | FileCheck %s
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; CHECK-ERROR: LLVM ERROR: OpPredicated[Load/Store]INTEL
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; CHECK-ERROR-SAME: instructions require the following SPIR-V extension: SPV_INTEL_predicated_io
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; CHECK-DAG: Capability PredicatedIOINTEL
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; CHECK-DAG: Extension "SPV_INTEL_predicated_io"
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; CHECK-DAG: %[[Int32Ty:[0-9]+]] = OpTypeInt 32 0
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; CHECK-DAG: %[[IntPtrTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[Int32Ty]]
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; CHECK-DAG: %[[BoolTy:[0-9]+]] = OpTypeBool
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; CHECK-DAG: %[[VoidTy:[0-9]+]] = OpTypeVoid
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; CHECK: %[[LoadPtr:[0-9]+]] = OpFunctionParameter %[[IntPtrTy]]
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; CHECK: %[[StorePtr:[0-9]+]] = OpFunctionParameter %[[IntPtrTy]]
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; CHECK: %[[DefaultVal:[0-9]+]] = OpFunctionParameter %[[Int32Ty]]
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; CHECK: %[[StoreObj:[0-9]+]] = OpFunctionParameter %[[Int32Ty]]
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; CHECK: %[[Predicate:[0-9]+]] = OpFunctionParameter %[[BoolTy]]
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; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]]
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; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] None
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; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]]
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; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] None
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define spir_func void @foo(ptr addrspace(1) %load_pointer, ptr addrspace(1) %store_pointer, i32 %default_value, i32 %store_object, i1 zeroext %predicate) {
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entry:
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%1 = call spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1) %load_pointer, i1 %predicate, i32 %default_value)
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%2 = call spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1) %load_pointer, i1 %predicate, i32 %default_value, i32 0)
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call spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1) %store_pointer, i32 %store_object, i1 %predicate)
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call spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1) %store_pointer, i32 %store_object, i1 %predicate, i32 0)
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ret void
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}
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declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1), i1, i32)
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declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1), i1, i32, i32)
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declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1), i32, i1)
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declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1), i32, i1, i32)
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