[AMDGPU] Further improve AMDGPUSubtargetFeature multiclass (#177077)
This PR extends the multiclass to support two additional parameters: one for specifying whether an `AssemblerPredicate` should be generated, and another for dependent `SubtargetFeatures`. This allows 15 more definitions to be converted to use the multiclass.
This commit is contained in:
Shilei Tian
GitHub
parent
d64d3735ab
commit
fa4f7657a2
@ -23,25 +23,51 @@ def p6 : PtrValueType<i32, 6>;
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// AMDGPU Subtarget Feature (device properties)
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//===----------------------------------------------------------------------===//
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// Multiclass to define a SubtargetFeature along with an optional predicate.
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// The predicate is generated when GenPredicate is 1 (default).
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// Usage: defm MadMixInsts : AMDGPUSubtargetFeature<"mad-mix-insts", "description">;
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// Multiclass to define a SubtargetFeature along with optional predicates.
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// Parameters:
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// - FeatureString: The feature string used in the SubtargetFeature.
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// - Description: The description of the feature.
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// - GenPredicate: If 1 (default), generates a Has#NAME predicate.
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// - GenAssemblerPredicate: If 1 (default), the predicate includes AssemblerPredicate.
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// - Deps: List of dependent SubtargetFeatures (default empty).
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//
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// Usage:
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// defm MadMixInsts : AMDGPUSubtargetFeature<"mad-mix-insts", "description">;
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// This generates:
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// - FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts", "HasMadMixInsts", "true", "description">
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// - HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">, AssemblerPredicate<(any_of FeatureMadMixInsts)>
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// - HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
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// AssemblerPredicate<(any_of FeatureMadMixInsts)>
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//
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// With GenAssemblerPredicate=0:
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// defm Foo : AMDGPUSubtargetFeature<"foo", "desc", 1, 0>;
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// This generates:
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// - FeatureFoo : SubtargetFeature<...>
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// - HasFoo : Predicate<"Subtarget->hasFoo()"> (no AssemblerPredicate)
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//
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// With dependencies:
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// defm Bar : AMDGPUSubtargetFeature<"bar", "desc", 1, 1, [FeatureFoo]>;
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// This generates:
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// - FeatureBar : SubtargetFeature<"bar", "HasBar", "true", "desc", [FeatureFoo]>
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// - HasBar : Predicate + AssemblerPredicate
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multiclass AMDGPUSubtargetFeature<string FeatureString,
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string Description,
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bit GenPredicate = 1> {
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bit GenPredicate = 1,
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bit GenAssemblerPredicate = 1,
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list<SubtargetFeature> Deps = []> {
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def Feature#NAME : SubtargetFeature<FeatureString,
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"Has"#NAME,
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"true",
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Description
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Description,
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Deps
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>;
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if GenPredicate then
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def Has#NAME
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: Predicate<"Subtarget->has"#NAME#"()">,
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AssemblerPredicate<(any_of !cast<SubtargetFeature>("Feature"#NAME))>;
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if GenAssemblerPredicate then
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def Has#NAME
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: Predicate<"Subtarget->has"#NAME#"()">,
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AssemblerPredicate<(any_of !cast<SubtargetFeature>("Feature"#NAME))>;
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else
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def Has#NAME : Predicate<"Subtarget->has"#NAME#"()">;
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}
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def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
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@ -152,7 +178,8 @@ def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
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def FeatureRelaxedBufferOOBMode : SubtargetFeature<"relaxed-buffer-oob-mode",
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"RelaxedBufferOOBMode",
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"true",
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"Disable strict out-of-bounds buffer guarantees. An OOB access may potentially cause an adjacent access to be treated as if it were also OOB"
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"Disable strict out-of-bounds buffer guarantees. An OOB access may potentially"
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"cause an adjacent access to be treated as if it were also OOB"
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>;
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defm ApertureRegs : AMDGPUSubtargetFeature<"aperture-regs",
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@ -334,7 +361,8 @@ def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-
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def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
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"NegativeUnalignedScratchOffsetBug",
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"true",
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"Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
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"Scratch instructions with a VGPR offset and a negative immediate offset that"
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"is not a multiple of 4 read wrong memory on GFX10"
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>;
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defm Offset3fBug : AMDGPUSubtargetFeature<"offset-3f-bug",
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@ -352,10 +380,10 @@ defm ImageGather4D16Bug : AMDGPUSubtargetFeature<"image-gather4-d16-bug",
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/*GenPredicate=*/0
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>;
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def FeatureMADIntraFwdBug : SubtargetFeature<"mad-intra-fwd-bug",
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"HasMADIntraFwdBug",
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"true",
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"MAD_U64/I64 intra instruction forwarding bug"
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defm MADIntraFwdBug : AMDGPUSubtargetFeature<"mad-intra-fwd-bug",
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"MAD_U64/I64 intra instruction forwarding bug",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/0
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>;
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defm MSAALoadDstSelBug : AMDGPUSubtargetFeature<"msaa-load-dst-sel-bug",
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@ -533,9 +561,7 @@ defm 16BitInsts : AMDGPUSubtargetFeature<"16-bit-insts",
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"Has i16/f16 instructions"
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>;
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def FeatureTrue16BitInsts : SubtargetFeature<"true16",
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"HasTrue16BitInsts",
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"true",
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defm True16BitInsts : AMDGPUSubtargetFeature<"true16",
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"True 16-bit operand instructions"
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>;
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@ -587,10 +613,10 @@ defm ScalarAtomics : AMDGPUSubtargetFeature<"scalar-atomics",
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"Has atomic scalar memory instructions"
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>;
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def FeatureSDWA : SubtargetFeature<"sdwa",
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"HasSDWA",
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"true",
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"Support SDWA (Sub-DWORD Addressing) extension"
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defm SDWA : AMDGPUSubtargetFeature<"sdwa",
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"Support SDWA (Sub-DWORD Addressing) extension",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/0
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>;
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defm SDWAOmod : AMDGPUSubtargetFeature<"sdwa-omod",
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@ -772,10 +798,10 @@ defm FP8E5M3Insts : AMDGPUSubtargetFeature<"fp8e5m3-insts",
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"Has fp8 e5m3 format support"
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>;
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def FeatureCvtFP8VOP1Bug : SubtargetFeature<"cvt-fp8-vop1-bug",
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"HasCvtFP8Vop1Bug",
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"true",
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defm CvtFP8VOP1Bug : AMDGPUSubtargetFeature<"cvt-fp8-vop1-bug",
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"FP8/BF8 VOP1 form of conversion to F32 is unreliable",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/0,
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[FeatureFP8ConversionInsts]
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>;
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@ -820,11 +846,11 @@ defm AtomicFlatPkAdd16Insts : AMDGPUSubtargetFeature<"atomic-flat-pk-add-16-inst
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"Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions"
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>;
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def FeatureAtomicFaddRtnInsts : SubtargetFeature<"atomic-fadd-rtn-insts",
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"HasAtomicFaddRtnInsts",
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"true",
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defm AtomicFaddRtnInsts : AMDGPUSubtargetFeature<"atomic-fadd-rtn-insts",
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"Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that "
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"return original value",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/1,
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[FeatureFlatGlobalInsts]
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>;
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@ -836,25 +862,25 @@ defm AtomicFMinFMaxF64GlobalInsts : AMDGPUSubtargetFeature<"atomic-fmin-fmax-glo
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"Has global/buffer instructions for atomicrmw fmin/fmax for float"
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>;
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def FeatureAtomicFMinFMaxF32FlatInsts : SubtargetFeature<"atomic-fmin-fmax-flat-f32",
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"HasAtomicFMinFMaxF32FlatInsts",
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"true",
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defm AtomicFMinFMaxF32FlatInsts : AMDGPUSubtargetFeature<"atomic-fmin-fmax-flat-f32",
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"Has flat memory instructions for atomicrmw fmin/fmax for float",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/1,
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[FeatureFlatAddressSpace]
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>;
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def FeatureAtomicFMinFMaxF64FlatInsts : SubtargetFeature<"atomic-fmin-fmax-flat-f64",
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"HasAtomicFMinFMaxF64FlatInsts",
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"true",
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defm AtomicFMinFMaxF64FlatInsts : AMDGPUSubtargetFeature<"atomic-fmin-fmax-flat-f64",
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"Has flat memory instructions for atomicrmw fmin/fmax for double",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/1,
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[FeatureFlatAddressSpace]
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>;
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def FeatureAtomicFaddNoRtnInsts : SubtargetFeature<"atomic-fadd-no-rtn-insts",
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"HasAtomicFaddNoRtnInsts",
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"true",
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defm AtomicFaddNoRtnInsts : AMDGPUSubtargetFeature<"atomic-fadd-no-rtn-insts",
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"Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that "
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"don't return original value",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/1,
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[FeatureFlatGlobalInsts]
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>;
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@ -867,37 +893,36 @@ def FeatureAtomicBufferGlobalPkAddF16NoRtnInsts
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[FeatureFlatGlobalInsts]
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>;
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def FeatureAtomicBufferGlobalPkAddF16Insts : SubtargetFeature<"atomic-buffer-global-pk-add-f16-insts",
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"HasAtomicBufferGlobalPkAddF16Insts",
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"true",
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"Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that "
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"can return original value",
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[FeatureFlatGlobalInsts]
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defm AtomicBufferGlobalPkAddF16Insts : AMDGPUSubtargetFeature<"atomic-buffer-global-pk-add-f16-insts",
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"Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that "
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"can return original value",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/1,
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[FeatureFlatGlobalInsts]
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>;
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def FeatureAtomicGlobalPkAddBF16Inst : SubtargetFeature<"atomic-global-pk-add-bf16-inst",
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"HasAtomicGlobalPkAddBF16Inst",
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"true",
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"Has global_atomic_pk_add_bf16 instruction",
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[FeatureFlatGlobalInsts]
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defm AtomicGlobalPkAddBF16Inst : AMDGPUSubtargetFeature<"atomic-global-pk-add-bf16-inst",
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"Has global_atomic_pk_add_bf16 instruction",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/1,
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[FeatureFlatGlobalInsts]
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>;
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defm AtomicBufferPkAddBF16Inst : AMDGPUSubtargetFeature<"atomic-buffer-pk-add-bf16-inst",
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"Has buffer_atomic_pk_add_bf16 instruction"
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>;
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def FeatureAtomicCSubNoRtnInsts : SubtargetFeature<"atomic-csub-no-rtn-insts",
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"HasAtomicCSubNoRtnInsts",
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"true",
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defm AtomicCSubNoRtnInsts : AMDGPUSubtargetFeature<"atomic-csub-no-rtn-insts",
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"Has buffer_atomic_csub and global_atomic_csub instructions that don't "
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"return original value"
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"return original value",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/0
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>;
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def FeatureFlatAtomicFaddF32Inst
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: SubtargetFeature<"flat-atomic-fadd-f32-inst",
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"HasFlatAtomicFaddF32Inst",
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"true",
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defm FlatAtomicFaddF32Inst : AMDGPUSubtargetFeature<"flat-atomic-fadd-f32-inst",
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"Has flat_atomic_add_f32 instruction",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/1,
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[FeatureFlatAddressSpace]
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>;
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@ -969,10 +994,10 @@ defm ShaderCyclesRegister : AMDGPUSubtargetFeature<"shader-cycles-register",
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"Has SHADER_CYCLES hardware register"
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>;
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def FeatureShaderCyclesHiLoRegisters : SubtargetFeature<"shader-cycles-hi-lo-registers",
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"HasShaderCyclesHiLoRegisters",
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"true",
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"Has SHADER_CYCLES_HI/LO hardware registers"
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defm ShaderCyclesHiLoRegisters : AMDGPUSubtargetFeature<"shader-cycles-hi-lo-registers",
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"Has SHADER_CYCLES_HI/LO hardware registers",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/0
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>;
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defm MadMacF32Insts : AMDGPUSubtargetFeature<"mad-mac-f32-insts",
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@ -1230,16 +1255,16 @@ defm ArchitectedSGPRs : AMDGPUSubtargetFeature<"architected-sgprs",
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/*GenPredicate=*/0
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>;
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def FeatureGDS : SubtargetFeature<"gds",
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"HasGDS",
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"true",
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"Has Global Data Share"
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defm GDS : AMDGPUSubtargetFeature<"gds",
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"Has Global Data Share",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/0
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>;
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def FeatureGWS : SubtargetFeature<"gws",
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"HasGWS",
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"true",
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"Has Global Wave Sync"
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defm GWS : AMDGPUSubtargetFeature<"gws",
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"Has Global Wave Sync",
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/*GenPredicate=*/1,
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/*GenAssemblerPredicate=*/0
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>;
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def FeatureRequiresCOV6 : SubtargetFeature<"requires-cov6",
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@ -2355,14 +2380,6 @@ def isGFX940orGFX1250 :
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def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
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AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
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def HasAtomicFMinFMaxF32FlatInsts :
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Predicate<"Subtarget->hasAtomicFMinFMaxF32FlatInsts()">,
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AssemblerPredicate<(any_of FeatureAtomicFMinFMaxF32FlatInsts)>;
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def HasAtomicFMinFMaxF64FlatInsts :
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Predicate<"Subtarget->hasAtomicFMinFMaxF64FlatInsts()">,
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AssemblerPredicate<(any_of FeatureAtomicFMinFMaxF64FlatInsts)>;
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def HasAtomicCondSubClampFlatInsts :
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Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
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AssemblerPredicate<(all_of FeatureGFX12Insts)>;
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@ -2432,8 +2449,6 @@ def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
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def HasXNACKEnabled : Predicate<"Subtarget->isXNACKEnabled()">;
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def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">,
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AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
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def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()">,
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AssemblerPredicate<(all_of (not FeatureTrue16BitInsts))>;
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@ -2466,8 +2481,6 @@ def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()
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def HasFminFmaxLegacy : Predicate<"Subtarget->hasFminFmaxLegacy()">;
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def HasSDWA : Predicate<"Subtarget->hasSDWA()">;
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def HasSDWA8 : Predicate<"Subtarget->hasSDWA()">,
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AssemblerPredicate<(all_of (not FeatureGFX9Insts), FeatureSDWA)>;
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@ -2518,8 +2531,6 @@ def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
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def NotHasMAIInsts : Predicate<"!Subtarget->hasMAIInsts()">,
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AssemblerPredicate<(all_of (not FeatureMAIInsts))>;
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def HasShaderCyclesHiLoRegisters : Predicate<"Subtarget->hasShaderCyclesHiLoRegisters()">;
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def NotHasFP8E5M3Insts : Predicate<"!Subtarget->hasFP8E5M3Insts()">,
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AssemblerPredicate<(all_of (not FeatureFP8E5M3Insts))>;
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@ -2533,23 +2544,9 @@ def HasAtomicDsCondSubClampInsts :
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Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
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AssemblerPredicate<(all_of FeatureGFX12Insts)>;
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def HasAtomicFaddRtnInsts : Predicate<"Subtarget->hasAtomicFaddRtnInsts()">,
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AssemblerPredicate<(all_of FeatureAtomicFaddRtnInsts)>;
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def HasAtomicFaddNoRtnInsts : Predicate<"Subtarget->hasAtomicFaddNoRtnInsts()">,
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AssemblerPredicate<(all_of FeatureAtomicFaddNoRtnInsts)>;
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def HasAtomicBufferGlobalPkAddF16NoRtnInsts
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: Predicate<"Subtarget->hasAtomicBufferGlobalPkAddF16NoRtnInsts() || Subtarget->hasAtomicBufferGlobalPkAddF16Insts()">,
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AssemblerPredicate<(any_of FeatureAtomicBufferGlobalPkAddF16NoRtnInsts, FeatureAtomicBufferGlobalPkAddF16Insts)>;
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def HasAtomicBufferGlobalPkAddF16Insts
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: Predicate<"Subtarget->hasAtomicBufferGlobalPkAddF16Insts()">,
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AssemblerPredicate<(all_of FeatureAtomicBufferGlobalPkAddF16Insts)>;
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def HasAtomicGlobalPkAddBF16Inst
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: Predicate<"Subtarget->hasAtomicGlobalPkAddBF16Inst()">,
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AssemblerPredicate<(all_of FeatureAtomicGlobalPkAddBF16Inst)>;
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def HasFlatAtomicFaddF32Inst
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: Predicate<"Subtarget->hasFlatAtomicFaddF32Inst()">,
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AssemblerPredicate<(all_of FeatureFlatAtomicFaddF32Inst)>;
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def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
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AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
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@ -2563,21 +2560,12 @@ def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
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def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
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AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
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def HasMADIntraFwdBug : Predicate<"Subtarget->hasMADIntraFwdBug()">;
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def HasNotMADIntraFwdBug : Predicate<"!Subtarget->hasMADIntraFwdBug()">;
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def NotHasMADIntraFwdBug : Predicate<"!Subtarget->hasMADIntraFwdBug()">;
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def NotHasSALUFloatInsts : Predicate<"!Subtarget->hasSALUFloatInsts()">,
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AssemblerPredicate<(all_of (not FeatureSALUFloatInsts))>;
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def HasGDS : Predicate<"Subtarget->hasGDS()">;
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def HasGWS : Predicate<"Subtarget->hasGWS()">;
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def HasCvtFP8VOP1Bug : Predicate<"Subtarget->hasCvtFP8VOP1Bug()">;
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def HasNoCvtFP8VOP1Bug : Predicate<"!Subtarget->hasCvtFP8VOP1Bug()">;
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def HasAtomicCSubNoRtnInsts : Predicate<"Subtarget->hasAtomicCSubNoRtnInsts()">;
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def NotHasCvtFP8VOP1Bug : Predicate<"!Subtarget->hasCvtFP8VOP1Bug()">;
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def NeedsAlignedVGPRs : Predicate<"Subtarget->needsAlignedVGPRs()">,
|
||||
AssemblerPredicate<(all_of FeatureRequiresAlignedVGPRs)>;
|
||||
|
||||
@ -75,7 +75,7 @@
|
||||
X(BVHDualAndBVH8Insts) \
|
||||
X(Clusters) \
|
||||
X(CubeInsts) \
|
||||
X(CvtFP8Vop1Bug) \
|
||||
X(CvtFP8VOP1Bug) \
|
||||
X(CvtNormInsts) \
|
||||
X(CvtPkNormVOP2Insts) \
|
||||
X(CvtPkNormVOP3Insts) \
|
||||
@ -1008,9 +1008,6 @@ public:
|
||||
// \returns true if the target has split barriers feature
|
||||
bool hasSplitBarriers() const { return getGeneration() >= GFX12; }
|
||||
|
||||
// \returns true if FP8/BF8 VOP1 form of conversion to F32 is unreliable.
|
||||
bool hasCvtFP8VOP1Bug() const { return HasCvtFP8Vop1Bug; }
|
||||
|
||||
// \returns true if CSUB (a.k.a. SUB_CLAMP on GFX12) atomics support a
|
||||
// no-return form.
|
||||
|
||||
|
||||
@ -670,7 +670,7 @@ let OtherPredicates = [HasCvtFP8VOP1Bug] in {
|
||||
(V_CVT_F32_BF8_sdwa 0, $src, 0, 0, 0)>;
|
||||
}
|
||||
|
||||
let OtherPredicates = [HasNoCvtFP8VOP1Bug, HasSDWA] in { // FIXME: HasSDWA is a substitute for !gfx12
|
||||
let OtherPredicates = [NotHasCvtFP8VOP1Bug, HasSDWA] in { // FIXME: HasSDWA is a substitute for !gfx12
|
||||
def : GCNPat<(f32 (int_amdgcn_cvt_f32_fp8 i32:$src, 0)),
|
||||
(V_CVT_F32_FP8_e32 $src)>;
|
||||
def : GCNPat<(f32 (int_amdgcn_cvt_f32_bf8 i32:$src, 0)),
|
||||
|
||||
@ -435,8 +435,8 @@ defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOPProfileMQSAD>;
|
||||
|
||||
let isCommutable = 1, SchedRW = [WriteIntMul, WriteSALU] in {
|
||||
let SubtargetPredicate = isGFX7Plus in {
|
||||
defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [HasNotMADIntraFwdBug]>;
|
||||
defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [HasNotMADIntraFwdBug]>;
|
||||
defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [NotHasMADIntraFwdBug]>;
|
||||
defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [NotHasMADIntraFwdBug]>;
|
||||
}
|
||||
let SubtargetPredicate = isGFX11Only, OtherPredicates = [HasMADIntraFwdBug],
|
||||
Constraints = "@earlyclobber $vdst" in {
|
||||
@ -1067,7 +1067,7 @@ multiclass IMAD32_Mul24_Pats<VOP3_Pseudo inst> {
|
||||
}
|
||||
|
||||
// exclude pre-GFX9 where it was slow
|
||||
let OtherPredicates = [HasNotMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in {
|
||||
let OtherPredicates = [NotHasMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in {
|
||||
defm : IMAD32_Pats<V_MAD_U64_U32_e64>;
|
||||
defm : IMAD32_Mul24_Pats<V_MAD_U64_U32_e64>;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user