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AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (#179778)

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vangthao95 2026-02-20 09:44:58 -08:00 committed by GitHub
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19 changed files with 6033 additions and 623 deletions
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23
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
View File

@ -1345,6 +1345,29 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
addRulesForGOpcs({G_FMINIMUM, G_FMAXIMUM}, Standard)
.Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}})
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}})
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
addRulesForGOpcs({G_FMINNUM_IEEE, G_FMAXNUM_IEEE, G_FMINNUM, G_FMAXNUM},
Standard)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}})
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
.Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}}, hasSALUFloat)
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}}, !hasSALUFloat)
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
addRulesForGOpcs({G_FPTRUNC})
.Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
.Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}})

4
llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 {
; GFX10-LABEL: test_fmed3_f32_known_nnan_ieee_true:

4
llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
define float @test_min_max_ValK0_K1_f32(float %a) #0 {
; GFX10-LABEL: test_min_max_ValK0_K1_f32:

6
llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
define float @test_min_max_ValK0_K1_f32(float %a) #0 {
; GFX10-LABEL: test_min_max_ValK0_K1_f32:

562
llvm/test/CodeGen/AMDGPU/fmaximum.ll
View File

@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) {
; GFX9-LABEL: test_fmaximum_f32_vv:
@ -24,14 +24,25 @@ define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) {
}
define amdgpu_ps float @test_fmaximum_f32_ss(float inreg %a, float inreg %b) {
; GFX9-LABEL: test_fmaximum_f32_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_max_f32_e32 v1, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
; GFX9-SDAG-LABEL: test_fmaximum_f32_ss:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX9-SDAG-NEXT: v_max_f32_e32 v1, s0, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_f32_ss:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7fc00000
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_f32_ss:
; GFX12: ; %bb.0:
@ -127,18 +138,36 @@ define amdgpu_ps <2 x float> @test_fmaximum_v2f32(<2 x float> %a, <2 x float> %b
}
define amdgpu_ps <2 x float> @test_fmaximum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) {
; GFX9-LABEL: test_fmaximum_v2f32_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_max_f32_e32 v1, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_max_f32_e32 v3, s1, v1
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
; GFX9-SDAG-LABEL: test_fmaximum_v2f32_ss:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX9-SDAG-NEXT: v_max_f32_e32 v1, s0, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX9-SDAG-NEXT: v_max_f32_e32 v3, s1, v1
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_v2f32_ss:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, s1, v0
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s1, v0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7fc00000
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7fc00000
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v2f32_ss:
; GFX12: ; %bb.0:
@ -315,14 +344,25 @@ define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) {
}
define amdgpu_ps half @test_fmaximum_f16_ss(half inreg %a, half inreg %b) {
; GFX9-LABEL: test_fmaximum_f16_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_max_f16_e32 v1, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
; GFX9-SDAG-LABEL: test_fmaximum_f16_ss:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX9-SDAG-NEXT: v_max_f16_e32 v1, s0, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_f16_ss:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: v_max_f16_e32 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7e00
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_f16_ss:
; GFX12: ; %bb.0:
@ -389,16 +429,23 @@ define amdgpu_ps <2 x half> @test_fmaximum_v2f16_ss(<2 x half> inreg %a, <2 x ha
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: s_lshr_b32 s1, s1, 16
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s0, 16
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s0, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s3, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s3, s2, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v2f16_ss:
@ -428,16 +475,19 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX9-GISEL-LABEL: test_fmaximum_v3f16_vv:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_pk_max_f16 v4, v0, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v4, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_pk_max_f16 v4, v1, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
; GFX9-GISEL-NEXT: v_pk_max_f16 v2, v1, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fmaximum_v3f16_vv:
@ -454,8 +504,11 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b
;
; GFX12-GISEL-FAKE16-LABEL: test_fmaximum_v3f16_vv:
; GFX12-GISEL-FAKE16: ; %bb.0:
; GFX12-GISEL-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-GISEL-FAKE16-NEXT: v_maximum_f16 v1, v1, v3
; GFX12-GISEL-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog
%val = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b)
ret <3 x half> %val
@ -490,19 +543,28 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s5
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX9-GISEL-NEXT: v_pk_max_f16 v3, s1, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v1
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s5
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s5, s2, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s1, v0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fmaximum_v3f16_ss:
@ -607,27 +669,41 @@ define amdgpu_ps <4 x half> @test_fmaximum_v4f16_ss(<4 x half> inreg %a, <4 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s2, 16
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
; GFX9-GISEL-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s3, 16
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: s_lshr_b32 s0, s1, 16
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s2
; GFX9-GISEL-NEXT: v_pk_max_f16 v2, s1, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s1, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, v2, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v4, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s5, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s5, s4, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s4, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: s_lshr_b32 s3, s3, 16
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s1, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s1, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s4, 0x7e00
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s1, s1, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v4f16_ss:
@ -685,15 +761,31 @@ define amdgpu_ps <2 x float> @test_fmaximum_f64_ss(double inreg %a, double inreg
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_f64_ss:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3]
; GFX12-NEXT: ; return to shader part epilog
; GFX12-SDAG-LABEL: test_fmaximum_f64_ss:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3]
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: test_fmaximum_f64_ss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call double @llvm.maximum.f64(double %a, double %b)
%ret = bitcast double %val to <2 x float>
ret <2 x float> %ret
@ -727,18 +819,43 @@ define amdgpu_ps <4 x float> @test_fmaximum_v2f64_ss(<2 x double> inreg %a, <2 x
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v5, s[0:1]
; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[4:5], s[4:5], s[2:3]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[6:7], s[2:3]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v2f64_ss:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5]
; GFX12-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7]
; GFX12-NEXT: ; return to shader part epilog
; GFX12-SDAG-LABEL: test_fmaximum_v2f64_ss:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5]
; GFX12-SDAG-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7]
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: test_fmaximum_v2f64_ss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5]
; GFX12-GISEL-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b)
%ret = bitcast <2 x double> %val to <4 x float>
ret <4 x float> %ret
@ -833,75 +950,152 @@ define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s9
; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s10
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s11
; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: s_mov_b32 s8, 0
; GFX9-GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s13
; GFX9-GISEL-NEXT: v_max_f64 v[6:7], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: s_cselect_b64 s[10:11], s[0:1], s[8:9]
; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s14
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s15
; GFX9-GISEL-NEXT: v_max_f64 v[8:9], s[6:7], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], s[6:7], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v10, v5, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v10, v7, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v8, s[4:5]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v10, v9, s[4:5]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[6:7], v[0:1]
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[6:7], v[0:1]
; GFX9-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[8:9]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[4:5], s[8:9]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s10
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s11
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, s4
; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, s5
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v4f64_ss:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9]
; GFX12-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11]
; GFX12-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13]
; GFX12-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15]
; GFX12-NEXT: ; return to shader part epilog
; GFX12-SDAG-LABEL: test_fmaximum_v4f64_ss:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9]
; GFX12-SDAG-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11]
; GFX12-SDAG-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13]
; GFX12-SDAG-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15]
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: test_fmaximum_v4f64_ss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9]
; GFX12-GISEL-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11]
; GFX12-GISEL-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13]
; GFX12-GISEL-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v6
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b)
%ret = bitcast <4 x double> %val to <8 x float>
ret <8 x float> %ret
}
define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
; GFX9-LABEL: fmaximumi_f32_move_to_valu:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f32_e32 v4, v1, v2
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
; GFX9-SDAG-LABEL: fmaximumi_f32_move_to_valu:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: global_load_dword v2, v0, s[6:7] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_max_f32_e32 v4, v1, v2
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-SDAG-NEXT: s_endpgm
;
; GFX12-LABEL: fmaximumi_f32_move_to_valu:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_maximum_f32 v1, v1, v2
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
; GFX9-GISEL-LABEL: fmaximumi_f32_move_to_valu:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: global_load_dword v2, v0, s[6:7] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v1, v2
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7fc00000
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-LABEL: fmaximumi_f32_move_to_valu:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: v_maximum_f32 v1, v1, v2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: fmaximumi_f32_move_to_valu:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-NEXT: s_maximum_f32 s2, s2, s3
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-GISEL-NEXT: s_endpgm
%a = load volatile float, ptr addrspace(1) %aptr, align 4
%b = load volatile float, ptr addrspace(1) %bptr, align 4
%v = call float @llvm.maximum.f32(float %a, float %b)
@ -910,22 +1104,44 @@ define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr
}
define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
; GFX9-LABEL: fmaximum_f16_move_to_valu:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f16_e32 v4, v1, v2
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
; GFX9-SDAG-LABEL: fmaximum_f16_move_to_valu:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT: global_load_ushort v1, v0, s[2:3] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: global_load_ushort v2, v0, s[6:7] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_max_f16_e32 v4, v1, v2
; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-SDAG-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-SDAG-NEXT: s_endpgm
;
; GFX9-GISEL-LABEL: fmaximum_f16_move_to_valu:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: global_load_ushort v1, v0, s[2:3] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: v_max_f16_e32 v2, s2, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v1
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7e00
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-TRUE16-LABEL: fmaximum_f16_move_to_valu:
; GFX12-SDAG-TRUE16: ; %bb.0:
@ -966,9 +1182,13 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-TRUE16-NEXT: s_maximum_f16 s2, s2, s3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
@ -983,7 +1203,11 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_maximum_f16 v1, v1, v2
; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-FAKE16-NEXT: s_maximum_f16 s2, s2, s3
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2
; GFX12-GISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-GISEL-FAKE16-NEXT: s_endpgm
%a = load volatile half, ptr addrspace(1) %aptr, align 4

2699
llvm/test/CodeGen/AMDGPU/fmaxnum.ll
View File

File diff suppressed because it is too large Load Diff

6
llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
View File

@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test no legal f16. Should just keep the cast to f32 and
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-GISEL %s
; Test legal f16, no f16 fmed3. Should expand to min/max sequence
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
; Legal f16 med3. InstCombine ought to shrink the f32 op to f16 so the codegen doesn't really matter for this.
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0

10
llvm/test/CodeGen/AMDGPU/fmed3.ll
View File

@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-SDAG %s
; RUN: llc -mtriple=amdgcn -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s
; RUN: llc -mtriple=amdgcn -global-isel=1 -new-reg-bank-select < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=VI-SDAG %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
define amdgpu_kernel void @v_test_nnan_input_fmed3_r_i_i_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {
; SI-SDAG-LABEL: v_test_nnan_input_fmed3_r_i_i_f32:

562
llvm/test/CodeGen/AMDGPU/fminimum.ll
View File

@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define amdgpu_ps float @test_fminimum_f32_vv(float %a, float %b) {
; GFX9-LABEL: test_fminimum_f32_vv:
@ -24,14 +24,25 @@ define amdgpu_ps float @test_fminimum_f32_vv(float %a, float %b) {
}
define amdgpu_ps float @test_fminimum_f32_ss(float inreg %a, float inreg %b) {
; GFX9-LABEL: test_fminimum_f32_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_min_f32_e32 v1, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
; GFX9-SDAG-LABEL: test_fminimum_f32_ss:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX9-SDAG-NEXT: v_min_f32_e32 v1, s0, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_f32_ss:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: v_min_f32_e32 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7fc00000
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_f32_ss:
; GFX12: ; %bb.0:
@ -127,18 +138,36 @@ define amdgpu_ps <2 x float> @test_fminimum_v2f32(<2 x float> %a, <2 x float> %b
}
define amdgpu_ps <2 x float> @test_fminimum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) {
; GFX9-LABEL: test_fminimum_v2f32_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_min_f32_e32 v1, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_min_f32_e32 v3, s1, v1
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
; GFX9-SDAG-LABEL: test_fminimum_v2f32_ss:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX9-SDAG-NEXT: v_min_f32_e32 v1, s0, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX9-SDAG-NEXT: v_min_f32_e32 v3, s1, v1
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_v2f32_ss:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: v_min_f32_e32 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_min_f32_e32 v1, s1, v0
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s1, v0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7fc00000
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7fc00000
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v2f32_ss:
; GFX12: ; %bb.0:
@ -315,14 +344,25 @@ define amdgpu_ps half @test_fminimum_f16_vv(half %a, half %b) {
}
define amdgpu_ps half @test_fminimum_f16_ss(half inreg %a, half inreg %b) {
; GFX9-LABEL: test_fminimum_f16_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_min_f16_e32 v1, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
; GFX9-SDAG-LABEL: test_fminimum_f16_ss:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX9-SDAG-NEXT: v_min_f16_e32 v1, s0, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_f16_ss:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: v_min_f16_e32 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7e00
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_f16_ss:
; GFX12: ; %bb.0:
@ -389,16 +429,23 @@ define amdgpu_ps <2 x half> @test_fminimum_v2f16_ss(<2 x half> inreg %a, <2 x ha
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: s_lshr_b32 s1, s1, 16
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s0, 16
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s0, v0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s0, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s3, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s3, s2, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v2f16_ss:
@ -428,16 +475,19 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX9-GISEL-LABEL: test_fminimum_v3f16_vv:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_pk_min_f16 v4, v0, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v4, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_pk_min_f16 v4, v1, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
; GFX9-GISEL-NEXT: v_pk_min_f16 v2, v1, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fminimum_v3f16_vv:
@ -454,8 +504,11 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b
;
; GFX12-GISEL-FAKE16-LABEL: test_fminimum_v3f16_vv:
; GFX12-GISEL-FAKE16: ; %bb.0:
; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v3
; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog
%val = call <3 x half> @llvm.minimum.v3f16(<3 x half> %a, <3 x half> %b)
ret <3 x half> %val
@ -490,19 +543,28 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s0, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s5
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX9-GISEL-NEXT: v_pk_min_f16 v3, s1, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v1
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s5
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s5, s2, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s1, v0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fminimum_v3f16_ss:
@ -607,27 +669,41 @@ define amdgpu_ps <4 x half> @test_fminimum_v4f16_ss(<4 x half> inreg %a, <4 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s2, 16
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s0, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
; GFX9-GISEL-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s3, 16
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: s_lshr_b32 s0, s1, 16
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s2
; GFX9-GISEL-NEXT: v_pk_min_f16 v2, s1, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s1, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, v2, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v4, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s5, v0
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s5, s4, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s0, s4, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: s_lshr_b32 s3, s3, 16
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s1, v0
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s1, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7e00
; GFX9-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s4, 0x7e00
; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s1, s1, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v4f16_ss:
@ -685,15 +761,31 @@ define amdgpu_ps <2 x float> @test_fminimum_f64_ss(double inreg %a, double inreg
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_f64_ss:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_minimum_f64 v[0:1], s[0:1], s[2:3]
; GFX12-NEXT: ; return to shader part epilog
; GFX12-SDAG-LABEL: test_fminimum_f64_ss:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], s[0:1], s[2:3]
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: test_fminimum_f64_ss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], s[0:1], s[2:3]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call double @llvm.minimum.f64(double %a, double %b)
%ret = bitcast double %val to <2 x float>
ret <2 x float> %ret
@ -727,18 +819,43 @@ define amdgpu_ps <4 x float> @test_fminimum_v2f64_ss(<2 x double> inreg %a, <2 x
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9-GISEL-NEXT: v_min_f64 v[4:5], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v5, s[0:1]
; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[4:5], s[4:5], s[2:3]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[6:7], s[2:3]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v2f64_ss:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_minimum_f64 v[0:1], s[0:1], s[4:5]
; GFX12-NEXT: v_minimum_f64 v[2:3], s[2:3], s[6:7]
; GFX12-NEXT: ; return to shader part epilog
; GFX12-SDAG-LABEL: test_fminimum_v2f64_ss:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], s[0:1], s[4:5]
; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], s[2:3], s[6:7]
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: test_fminimum_v2f64_ss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], s[0:1], s[4:5]
; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], s[2:3], s[6:7]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)
%ret = bitcast <2 x double> %val to <4 x float>
ret <4 x float> %ret
@ -833,75 +950,152 @@ define amdgpu_ps <8 x float> @test_fminimum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s9
; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s10
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s11
; GFX9-GISEL-NEXT: v_min_f64 v[4:5], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
; GFX9-GISEL-NEXT: s_mov_b32 s8, 0
; GFX9-GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s13
; GFX9-GISEL-NEXT: v_min_f64 v[6:7], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: s_cselect_b64 s[10:11], s[0:1], s[8:9]
; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[4:5], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s14
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s15
; GFX9-GISEL-NEXT: v_min_f64 v[8:9], s[6:7], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], s[6:7], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v10, v5, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v10, v7, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v8, s[4:5]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v10, v9, s[4:5]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX9-GISEL-NEXT: v_min_f64 v[4:5], s[6:7], v[0:1]
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[6:7], v[0:1]
; GFX9-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[8:9]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[4:5], s[8:9]
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s10
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s11
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, s4
; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, s5
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v4f64_ss:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_minimum_f64 v[0:1], s[0:1], s[8:9]
; GFX12-NEXT: v_minimum_f64 v[2:3], s[2:3], s[10:11]
; GFX12-NEXT: v_minimum_f64 v[4:5], s[4:5], s[12:13]
; GFX12-NEXT: v_minimum_f64 v[6:7], s[6:7], s[14:15]
; GFX12-NEXT: ; return to shader part epilog
; GFX12-SDAG-LABEL: test_fminimum_v4f64_ss:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], s[0:1], s[8:9]
; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], s[2:3], s[10:11]
; GFX12-SDAG-NEXT: v_minimum_f64 v[4:5], s[4:5], s[12:13]
; GFX12-SDAG-NEXT: v_minimum_f64 v[6:7], s[6:7], s[14:15]
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: test_fminimum_v4f64_ss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], s[0:1], s[8:9]
; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], s[2:3], s[10:11]
; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], s[4:5], s[12:13]
; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], s[6:7], s[14:15]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v6
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <4 x double> @llvm.minimum.v4f64(<4 x double> %a, <4 x double> %b)
%ret = bitcast <4 x double> %val to <8 x float>
ret <8 x float> %ret
}
define amdgpu_kernel void @fminimumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
; GFX9-LABEL: fminimumi_f32_move_to_valu:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_min_f32_e32 v4, v1, v2
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
; GFX9-SDAG-LABEL: fminimumi_f32_move_to_valu:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: global_load_dword v2, v0, s[6:7] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_min_f32_e32 v4, v1, v2
; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-SDAG-NEXT: s_endpgm
;
; GFX12-LABEL: fminimumi_f32_move_to_valu:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_minimum_f32 v1, v1, v2
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
; GFX9-GISEL-LABEL: fminimumi_f32_move_to_valu:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: global_load_dword v2, v0, s[6:7] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v1, v2
; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v3
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7fc00000
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-LABEL: fminimumi_f32_move_to_valu:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: v_minimum_f32 v1, v1, v2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: fminimumi_f32_move_to_valu:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-NEXT: s_minimum_f32 s2, s2, s3
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-GISEL-NEXT: s_endpgm
%a = load volatile float, ptr addrspace(1) %aptr, align 4
%b = load volatile float, ptr addrspace(1) %bptr, align 4
%v = call float @llvm.minimum.f32(float %a, float %b)
@ -910,22 +1104,44 @@ define amdgpu_kernel void @fminimumi_f32_move_to_valu(ptr addrspace(1) %out, ptr
}
define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
; GFX9-LABEL: fminimum_f16_move_to_valu:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_min_f16_e32 v4, v1, v2
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
; GFX9-SDAG-LABEL: fminimum_f16_move_to_valu:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT: global_load_ushort v1, v0, s[2:3] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: global_load_ushort v2, v0, s[6:7] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_min_f16_e32 v4, v1, v2
; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-SDAG-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-SDAG-NEXT: s_endpgm
;
; GFX9-GISEL-LABEL: fminimum_f16_move_to_valu:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: global_load_ushort v1, v0, s[2:3] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT: v_min_f16_e32 v2, s2, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v1
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7e00
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-TRUE16-LABEL: fminimum_f16_move_to_valu:
; GFX12-SDAG-TRUE16: ; %bb.0:
@ -966,9 +1182,13 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-TRUE16-NEXT: s_minimum_f16 s2, s2, s3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
@ -983,7 +1203,11 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v2
; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-FAKE16-NEXT: s_minimum_f16 s2, s2, s3
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2
; GFX12-GISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-GISEL-FAKE16-NEXT: s_endpgm
%a = load volatile half, ptr addrspace(1) %aptr, align 4

2611
llvm/test/CodeGen/AMDGPU/fminnum.ll
View File

File diff suppressed because it is too large Load Diff

2
llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SDAG %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-GISEL %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-GISEL %s
; --------------------------------------------------------------------------------
; fminimum tests

37
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
View File

@ -6,11 +6,11 @@
; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=SDAG-CI %s
; FIXME-TRUE16. fix gisel
; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
; XUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %src1, half %src2) #0 {
; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
@ -414,12 +414,12 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; GFX9-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX9-NEXT: s_setpc_b64 s[30:31]
; SDAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; SDAG-GFX9: ; %bb.0:
; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; SDAG-GFX9-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; VI: ; %bb.0:
@ -446,11 +446,22 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-NEXT: v_and_b32_e64 v1, 0xffff, s0
; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GISEL-GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; GISEL-GFX9: ; %bb.0:
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; GISEL-GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xffff
; GISEL-GFX9-NEXT: v_and_b32_e32 v1, s4, v1
; GISEL-GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

64
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
View File

@ -7,12 +7,12 @@
; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=SDAG-CI %s
; FIXME-TRUE16. enable gisel
; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
; XUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
define half @mixlo_simple(float %src0, float %src1, float %src2) #0 {
; GFX1100-LABEL: mixlo_simple:
@ -627,19 +627,23 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; GISEL-GFX1100-LABEL: v_mad_mix_v3f32:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v6
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1]
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
; GISEL-GFX900-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GISEL-GFX900-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GISEL-GFX900-NEXT: v_lshl_or_b32 v1, s4, 16, v0
; GISEL-GFX900-NEXT: v_mov_b32_e32 v0, v6
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
@ -647,8 +651,10 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; GISEL-GFX906: ; %bb.0:
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
; GISEL-GFX906-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GISEL-GFX906-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GISEL-GFX906-NEXT: v_lshl_or_b32 v1, s4, 16, v0
; GISEL-GFX906-NEXT: v_mov_b32_e32 v0, v6
; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
;
@ -1192,20 +1198,23 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_postcvt:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GISEL-GFX1100-NEXT: v_pk_max_f16 v1, v1, v1 clamp
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v6
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_postcvt:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GISEL-GFX900-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX900-NEXT: v_mad_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_pk_max_f16 v1, v1, v1 clamp
; GISEL-GFX900-NEXT: v_mov_b32_e32 v0, v3
@ -1215,7 +1224,9 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; GISEL-GFX906: ; %bb.0:
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GISEL-GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX906-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_pk_max_f16 v1, v1, v1 clamp
; GISEL-GFX906-NEXT: v_mov_b32_e32 v0, v3
@ -2148,15 +2159,18 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_precvt:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v6
; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v1
; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v3
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-GFX1100-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v2, v0
; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_precvt:
@ -2164,11 +2178,12 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: v_mad_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_mad_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_cvt_f16_f32_e32 v2, v6
; GISEL-GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1
; GISEL-GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
; GISEL-GFX900-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX906-LABEL: v_mad_mix_v3f32_clamp_precvt:
@ -2176,11 +2191,12 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_cvt_f16_f32_e32 v2, v6
; GISEL-GFX906-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_cvt_f16_f32_e32 v1, v1
; GISEL-GFX906-NEXT: v_pack_b32_f16 v0, v2, v0
; GISEL-GFX906-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: v_mad_mix_v3f32_clamp_precvt:

14
llvm/test/CodeGen/AMDGPU/mad-mix.ll
View File

@ -8,13 +8,13 @@
; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,SDAG-CI %s
; FIXME-TRUE16. enable gisel
; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx9-generic --amdhsa-code-object-version=6 < %s | FileCheck -check-prefixes=GFX9GEN,GISEL-GFX9GEN %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,GISEL-CI %s
; XUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx9-generic --amdhsa-code-object-version=6 < %s | FileCheck -check-prefixes=GFX9GEN,GISEL-GFX9GEN %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,GISEL-CI %s
define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo:

4
llvm/test/CodeGen/AMDGPU/minimummaximum.ll
View File

@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-FAKE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-TRUE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-FAKE16 %s
define amdgpu_ps float @test_minmax_f32(float %a, float %b, float %c) {
; GFX12-LABEL: test_minmax_f32:

12
llvm/test/CodeGen/AMDGPU/minmax.ll
View File

@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-FAKE16 %s
define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) {
; GFX11-LABEL: test_minmax_i32:

16
llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
View File

@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_fmax_v2half:

16
llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
View File

@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_fmin_v2half:

4
llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
View File

@ -7,8 +7,8 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v2half: