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[RISC-V][MC] Introduce RVY extension feature

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This adds the initial feature for the base RVY extension,
other extensions such as the hybrid mode will be added later.
RVY specification: https://riscv.github.io/riscv-cheri/

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Petr Vesely <petr.vesely@codasip.com>

Pull Request: https://github.com/llvm/llvm-project/pull/176870
This commit is contained in:
Alexander Richardson 2026-01-25 22:05:31 -08:00 committed by GitHub
parent 313bec1c9a
commit fc2230f574
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5 changed files with 11 additions and 0 deletions
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1
clang/test/Driver/print-supported-extensions-riscv.c
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@ -241,6 +241,7 @@
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-NEXT: p 0.18 'P' ('Base P' (Packed SIMD))
// CHECK-NEXT: y 0.96 'Y' ('Base Y' (CHERI))
// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate)
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)

6
llvm/lib/Target/RISCV/RISCVFeatures.td
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@ -1123,6 +1123,12 @@ def HasStdExtZbkbOrP
"'Zbkb' (Bitmanip instructions for Cryptography) or "
"'Base P' (Packed-SIMD)">;
// "Y" extension (CHERI support)
def FeatureStdExtY : RISCVExperimentalExtension<0, 96, "'Base Y' (CHERI)">;
def HasStdExtY : Predicate<"Subtarget->hasStdExtY()">,
AssemblerPredicate<(all_of FeatureStdExtY), "'Base Y' (CHERI)">;
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//

2
llvm/test/CodeGen/RISCV/attributes.ll
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@ -301,6 +301,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-y %s -o - | FileCheck --check-prefix=RV64Y %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV64ZIBI %s
@ -618,6 +619,7 @@
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
; RV64P: .attribute 5, "rv64i2p1_p0p18"
; RV64Y: .attribute 5, "rv64i2p1_y0p96"
; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1"
; RVI20U32: .attribute 5, "rv32i2p1"

1
llvm/test/CodeGen/RISCV/features-info.ll
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@ -34,6 +34,7 @@
; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs).
; CHECK-NEXT: experimental-y - 'Y' ('Base Y' (CHERI)).
; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate).
; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad).
; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack).

1
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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@ -1393,6 +1393,7 @@ R"(All available -march extensions for RISC-V
Experimental extensions
p 0.18
y 0.96
zibi 0.1
zicfilp 1.0 This is a long dummy description
zicfiss 1.0