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[AMDGPU] Disable inline constants for pseudo scalar transcendentals (#104395)

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Prevent operand folding from inlining constants into pseudo scalar
transcendental f16 instructions.
However still allow literal constants.
This commit is contained in:
Carl Ritson 2024-08-17 16:52:38 +09:00 committed by GitHub
parent cb7614e839
commit fc6300a5f7
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4 changed files with 138 additions and 0 deletions
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6
llvm/lib/Target/AMDGPU/GCNSubtarget.h
View File

@ -1289,6 +1289,12 @@ public:
/// and STOREcnt rather than VMcnt, LGKMcnt and VScnt respectively.
bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; }
/// \returns true if inline constants are not supported for F16 pseudo
/// scalar transcendentals.
bool hasNoF16PseudoScalarTransInlineConstants() const {
return getGeneration() == GFX12;
}
/// \returns The maximum number of instructions that can be enclosed in an
/// S_CLAUSE on the given subtarget, or 0 for targets that do not support that
/// instruction.

4
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -5776,6 +5776,10 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
return false;
}
}
} else if (ST.hasNoF16PseudoScalarTransInlineConstants() && !MO->isReg() &&
isF16PseudoScalarTrans(MI.getOpcode()) &&
isInlineConstant(*MO, OpInfo)) {
return false;
}
if (MO->isReg()) {

8
llvm/lib/Target/AMDGPU/SIInstrInfo.h
View File

@ -946,6 +946,14 @@ public:
Opcode == AMDGPU::DS_GWS_BARRIER;
}
static bool isF16PseudoScalarTrans(unsigned Opcode) {
return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
Opcode == AMDGPU::V_S_LOG_F16_e64 ||
Opcode == AMDGPU::V_S_RCP_F16_e64 ||
Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
Opcode == AMDGPU::V_S_SQRT_F16_e64;
}
static bool doesNotReadTiedSource(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
}

120
llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir Normal file
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@ -0,0 +1,120 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# Do not use inline constants for f16 pseudo scalar transcendentals.
# But allow literal constants.
---
name: exp_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: exp_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: exp_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: exp_f16_literal
; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: log_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: log_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: log_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: log_f16_literal
; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rcp_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rcp_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rcp_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rcp_f16_literal
; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rsq_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rsq_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rsq_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rsq_f16_literal
; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: sqrt_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: sqrt_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: sqrt_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: sqrt_f16_literal
; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...