diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 95282c7c1455..19c942faf3c3 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -42930,7 +42930,6 @@ bool X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode( bool PoisonOnly, unsigned Depth) const { unsigned NumElts = DemandedElts.getBitWidth(); - // TODO: Add more target shuffles. switch (Op.getOpcode()) { case X86ISD::PSHUFD: case X86ISD::VPERMILPI: { @@ -42966,8 +42965,12 @@ bool X86TargetLowering::canCreateUndefOrPoisonForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const { - // TODO: Add more target shuffles. switch (Op.getOpcode()) { + // SSE vector shifts handle out of bounds shift amounts. + case X86ISD::VSHLI: + case X86ISD::VSRLI: + case X86ISD::VSRAI: + return false; case X86ISD::PSHUFD: case X86ISD::VPERMILPI: case X86ISD::UNPCKH: diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll index dbc027495297..1209e2633c06 100644 --- a/llvm/test/CodeGen/X86/freeze-binary.ll +++ b/llvm/test/CodeGen/X86/freeze-binary.ll @@ -546,9 +546,8 @@ define <8 x i16> @freeze_ashr_vec(<8 x i16> %a0) nounwind { define <4 x i32> @freeze_ashr_vec_outofrange(<4 x i32> %a0) nounwind { ; X86-LABEL: freeze_ashr_vec_outofrange: ; X86: # %bb.0: -; X86-NEXT: psrad $1, %xmm0 ; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,3] -; X86-NEXT: psrad $2, %xmm0 +; X86-NEXT: psrad $3, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_ashr_vec_outofrange: @@ -660,9 +659,8 @@ define <8 x i16> @freeze_lshr_vec(<8 x i16> %a0) nounwind { define <4 x i32> @freeze_lshr_vec_outofrange(<4 x i32> %a0) nounwind { ; X86-LABEL: freeze_lshr_vec_outofrange: ; X86: # %bb.0: -; X86-NEXT: psrld $1, %xmm0 ; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,3] -; X86-NEXT: psrld $2, %xmm0 +; X86-NEXT: psrld $3, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_lshr_vec_outofrange: