From fd6f16fab9ff8317bea72f2b770cdda26cfe514d Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 24 May 2010 17:42:55 +0000 Subject: [PATCH] SubRegIndex'ize MSP430 llvm-svn: 104513 --- llvm/lib/Target/MSP430/MSP430RegisterInfo.td | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td index 4078626ea2dd..db3f0e789abb 100644 --- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td @@ -65,7 +65,10 @@ def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW, [PCB, SPB, SRB, CGB, FPB, R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; -def subreg_8bit : PatLeaf<(i32 1)>; +def subreg_8bit : SubRegIndex { + let NumberHack = 1; + let Namespace = "MSP430"; +} def GR8 : RegisterClass<"MSP430", [i8], 8, // Volatile registers