shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

[Clang][AArch64] Fix typo with colon-separated syntax for system registers (#105608)

Browse Source 
The range for Op0 was set to 1 instead of 3.

The description of e493f177eeee84a9c6000ca7c92499233490f1d1 visually
explains the encoding of implementation-defined system registers.


796787d07c/llvm/lib/Target/AArch64/AArch64SystemOperands.td (L658-L674)

Gobolt: https://godbolt.org/z/WK9PqPvGE

Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>
This commit is contained in:
Robert Dazi 2025-03-10 13:05:41 +01:00 committed by GitHub
parent 502385c241
commit fdc8e5ab62
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 11 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
clang/lib/Sema/SemaARM.cpp
View File

@ -249,16 +249,16 @@ bool SemaARM::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,
}
}
SmallVector<int, 5> Ranges;
SmallVector<int, 5> FieldBitWidths;
if (FiveFields)
Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7});
FieldBitWidths.append({IsAArch64Builtin ? 2 : 4, 3, 4, 4, 3});
else
Ranges.append({15, 7, 15});
FieldBitWidths.append({4, 3, 4});
for (unsigned i = 0; i < Fields.size(); ++i) {
int IntField;
ValidString &= !Fields[i].getAsInteger(10, IntField);
ValidString &= (IntField >= 0 && IntField <= Ranges[i]);
ValidString &= (IntField >= 0 && IntField < (1 << FieldBitWidths[i]));
}
if (!ValidString)

7
clang/test/Sema/aarch64-special-register.c
View File

@ -116,6 +116,13 @@ unsigned long rsr64_6(void) {
return __builtin_arm_rsr64("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
}
void rsr64_7(unsigned long *r) {
// The following three instructions should produce the same assembly.
r[0] = __builtin_arm_rsr64("ICC_CTLR_EL3");
r[1] = __builtin_arm_rsr64("s3_6_c12_c12_4");
r[2] = __builtin_arm_rsr64("3:6:12:12:4");
}
__uint128_t rsr128_3(void) {
return __builtin_arm_rsr128("0:1:2"); //expected-error {{invalid special register for builtin}}
}