[AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122)
Add GlobalISel lowering of G_FMINIMUM and G_FMAXIMUM following the same logic as in SDag's expandFMINIMUM_FMAXIMUM. Update AMDGPU legalization rules: Pre GFX12 now uses new lowering method and make G_FMINNUM_IEEE and G_FMAXNUM_IEEE legal to match SDag.
This commit is contained in:
Mirko Brkušanin
GitHub
parent
26db21400d
commit
fe5f49942e
@ -497,6 +497,7 @@ public:
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LLVM_ABI LegalizeResult lowerMinMax(MachineInstr &MI);
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LLVM_ABI LegalizeResult lowerFCopySign(MachineInstr &MI);
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LLVM_ABI LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
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LLVM_ABI LegalizeResult lowerFMinimumMaximum(MachineInstr &MI);
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LLVM_ABI LegalizeResult lowerFMad(MachineInstr &MI);
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LLVM_ABI LegalizeResult lowerIntrinsicRound(MachineInstr &MI);
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LLVM_ABI LegalizeResult lowerFFloor(MachineInstr &MI);
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@ -4748,6 +4748,9 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
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case G_FMINIMUMNUM:
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case G_FMAXIMUMNUM:
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return lowerFMinNumMaxNum(MI);
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case G_FMINIMUM:
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case G_FMAXIMUM:
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return lowerFMinimumMaximum(MI);
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case G_MERGE_VALUES:
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return lowerMergeValues(MI);
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case G_UNMERGE_VALUES:
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@ -8777,6 +8780,77 @@ LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerFMinimumMaximum(MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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auto [Dst, Src0, Src1] = MI.getFirst3Regs();
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LLT Ty = MRI.getType(Dst);
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LLT CmpTy = Ty.changeElementSize(1);
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bool IsMax = (Opc == TargetOpcode::G_FMAXIMUM);
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unsigned OpcIeee =
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IsMax ? TargetOpcode::G_FMAXNUM_IEEE : TargetOpcode::G_FMINNUM_IEEE;
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unsigned OpcNonIeee =
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IsMax ? TargetOpcode::G_FMAXNUM : TargetOpcode::G_FMINNUM;
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bool MinMaxMustRespectOrderedZero = false;
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Register Res;
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// IEEE variants don't need canonicalization
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if (LI.isLegalOrCustom({OpcIeee, Ty})) {
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Res = MIRBuilder.buildInstr(OpcIeee, {Ty}, {Src0, Src1}).getReg(0);
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MinMaxMustRespectOrderedZero = true;
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} else if (LI.isLegalOrCustom({OpcNonIeee, Ty})) {
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Res = MIRBuilder.buildInstr(OpcNonIeee, {Ty}, {Src0, Src1}).getReg(0);
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} else {
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auto Compare = MIRBuilder.buildFCmp(
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IsMax ? CmpInst::FCMP_OGT : CmpInst::FCMP_OLT, CmpTy, Src0, Src1);
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Res = MIRBuilder.buildSelect(Ty, Compare, Src0, Src1).getReg(0);
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}
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// Propagate any NaN of both operands
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if (!MI.getFlag(MachineInstr::FmNoNans) &&
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(!isKnownNeverNaN(Src0, MRI) || isKnownNeverNaN(Src1, MRI))) {
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auto IsOrdered = MIRBuilder.buildFCmp(CmpInst::FCMP_ORD, CmpTy, Src0, Src1);
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LLT ElementTy = Ty.isScalar() ? Ty : Ty.getElementType();
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APFloat NaNValue = APFloat::getNaN(getFltSemanticForLLT(ElementTy));
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Register NaN = MIRBuilder.buildFConstant(ElementTy, NaNValue).getReg(0);
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if (Ty.isVector())
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NaN = MIRBuilder.buildSplatBuildVector(Ty, NaN).getReg(0);
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Res = MIRBuilder.buildSelect(Ty, IsOrdered, Res, NaN).getReg(0);
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}
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// fminimum/fmaximum requires -0.0 less than +0.0
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if (!MinMaxMustRespectOrderedZero && !MI.getFlag(MachineInstr::FmNsz)) {
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GISelValueTracking VT(MIRBuilder.getMF());
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KnownFPClass Src0Info = VT.computeKnownFPClass(Src0, fcZero);
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KnownFPClass Src1Info = VT.computeKnownFPClass(Src1, fcZero);
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if (!Src0Info.isKnownNeverZero() && !Src1Info.isKnownNeverZero()) {
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const unsigned Flags = MI.getFlags();
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Register Zero = MIRBuilder.buildFConstant(Ty, 0.0).getReg(0);
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auto IsZero = MIRBuilder.buildFCmp(CmpInst::FCMP_OEQ, CmpTy, Res, Zero);
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unsigned TestClass = IsMax ? fcPosZero : fcNegZero;
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auto LHSTestZero = MIRBuilder.buildIsFPClass(CmpTy, Src0, TestClass);
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auto LHSSelect =
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MIRBuilder.buildSelect(Ty, LHSTestZero, Src0, Res, Flags);
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auto RHSTestZero = MIRBuilder.buildIsFPClass(CmpTy, Src1, TestClass);
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auto RHSSelect =
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MIRBuilder.buildSelect(Ty, RHSTestZero, Src1, LHSSelect, Flags);
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Res = MIRBuilder.buildSelect(Ty, IsZero, RHSSelect, Res, Flags).getReg(0);
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}
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}
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MIRBuilder.buildCopy(Dst, Res);
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MI.eraseFromParent();
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return Legalized;
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}
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LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
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// Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
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Register DstReg = MI.getOperand(0).getReg();
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@ -976,9 +976,25 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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FPOpActions.clampMaxNumElementsStrict(0, S32, 2);
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}
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auto &MinNumMaxNumIeee =
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getActionDefinitionsBuilder({G_FMINNUM_IEEE, G_FMAXNUM_IEEE});
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if (ST.hasVOP3PInsts()) {
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MinNumMaxNumIeee.legalFor(FPTypesPK16)
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.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
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.clampMaxNumElements(0, S16, 2)
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.clampScalar(0, S16, S64)
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.scalarize(0);
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} else if (ST.has16BitInsts()) {
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MinNumMaxNumIeee.legalFor(FPTypes16).clampScalar(0, S16, S64).scalarize(0);
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} else {
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MinNumMaxNumIeee.legalFor(FPTypesBase)
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.clampScalar(0, S32, S64)
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.scalarize(0);
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}
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auto &MinNumMaxNum = getActionDefinitionsBuilder(
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{G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM, G_FMINNUM_IEEE,
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G_FMAXNUM_IEEE});
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{G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM});
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if (ST.hasVOP3PInsts()) {
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MinNumMaxNum.customFor(FPTypesPK16)
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@ -2136,9 +2152,17 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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.legalFor(FPTypesPK16)
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.clampMaxNumElements(0, S16, 2)
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.scalarize(0);
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} else if (ST.hasVOP3PInsts()) {
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getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
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.lowerFor({V2S16})
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.clampMaxNumElementsStrict(0, S16, 2)
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.scalarize(0)
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.lower();
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} else {
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// TODO: Implement
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getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM}).lower();
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getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
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.scalarize(0)
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.clampScalar(0, S32, S64)
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.lower();
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}
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getActionDefinitionsBuilder({G_MEMCPY, G_MEMCPY_INLINE, G_MEMMOVE, G_MEMSET})
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@ -2195,8 +2219,6 @@ bool AMDGPULegalizerInfo::legalizeCustom(
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case TargetOpcode::G_FMAXNUM:
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case TargetOpcode::G_FMINIMUMNUM:
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case TargetOpcode::G_FMAXIMUMNUM:
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case TargetOpcode::G_FMINNUM_IEEE:
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case TargetOpcode::G_FMAXNUM_IEEE:
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return legalizeMinNumMaxNum(Helper, MI);
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case TargetOpcode::G_EXTRACT_VECTOR_ELT:
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return legalizeExtractVectorElt(MI, MRI, B);
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@ -2817,23 +2839,8 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
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MachineFunction &MF = Helper.MIRBuilder.getMF();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const bool IsIEEEOp = MI.getOpcode() == AMDGPU::G_FMINNUM_IEEE ||
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MI.getOpcode() == AMDGPU::G_FMAXNUM_IEEE;
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// With ieee_mode disabled, the instructions have the correct behavior
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// already for G_FMINIMUMNUM/G_FMAXIMUMNUM.
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//
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// FIXME: G_FMINNUM/G_FMAXNUM should match the behavior with ieee_mode
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// enabled.
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if (!MFI->getMode().IEEE) {
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if (MI.getOpcode() == AMDGPU::G_FMINIMUMNUM ||
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MI.getOpcode() == AMDGPU::G_FMAXIMUMNUM)
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return true;
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return !IsIEEEOp;
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}
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if (IsIEEEOp)
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// With ieee_mode disabled, the instructions have the correct behavior.
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if (!MFI->getMode().IEEE)
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return true;
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return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized;
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275
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
Normal file
275
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
Normal file
@ -0,0 +1,275 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GFX12 %s
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---
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name: test_fmaximum_f16
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX9-LABEL: name: test_fmaximum_f16
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[TRUNC]], [[TRUNC1]]
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; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC1]]
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; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
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; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
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; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[SELECT]](s16)
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; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
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; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
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; GFX9-NEXT: SI_RETURN implicit $vgpr0
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;
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; GFX12-LABEL: name: test_fmaximum_f16
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; GFX12: liveins: $vgpr0, $vgpr1
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; GFX12-NEXT: {{ $}}
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; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s16) = G_FMAXIMUM [[TRUNC]], [[TRUNC1]]
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; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAXIMUM]](s16)
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; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
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; GFX12-NEXT: SI_RETURN implicit $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0(s32)
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%2:_(s32) = COPY $vgpr1
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%3:_(s16) = G_TRUNC %2(s32)
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%4:_(s16) = G_FMAXIMUM %1, %3
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%5:_(s32) = G_ANYEXT %4(s16)
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$vgpr0 = COPY %5(s32)
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SI_RETURN implicit $vgpr0
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...
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---
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name: test_fmaximum_f32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX9-LABEL: name: test_fmaximum_f32
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
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; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
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; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
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; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
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; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
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; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
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; GFX9-NEXT: SI_RETURN implicit $vgpr0
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;
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; GFX12-LABEL: name: test_fmaximum_f32
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; GFX12: liveins: $vgpr0, $vgpr1
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; GFX12-NEXT: {{ $}}
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; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY]], [[COPY1]]
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; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
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; GFX12-NEXT: SI_RETURN implicit $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = G_FMAXIMUM %0, %1
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$vgpr0 = COPY %2(s32)
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SI_RETURN implicit $vgpr0
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...
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---
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name: test_fmaximum_f64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GFX9-LABEL: name: test_fmaximum_f64
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; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
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; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]]
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; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
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; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
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; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
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; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
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; GFX9-NEXT: SI_RETURN implicit $vgpr0_vgpr1
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;
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; GFX12-LABEL: name: test_fmaximum_f64
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; GFX12: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GFX12-NEXT: {{ $}}
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; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s64) = G_FMAXIMUM [[COPY]], [[COPY1]]
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; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[FMAXIMUM]](s64)
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; GFX12-NEXT: SI_RETURN implicit $vgpr0_vgpr1
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = COPY $vgpr2_vgpr3
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%2:_(s64) = G_FMAXIMUM %0, %1
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$vgpr0_vgpr1 = COPY %2(s64)
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SI_RETURN implicit $vgpr0_vgpr1
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...
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---
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name: test_fmaximum_v2f16
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX9-LABEL: name: test_fmaximum_v2f16
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
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; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
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; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
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; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
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; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
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; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
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; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
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; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC2]]
|
||||
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC1]](s16), [[TRUNC3]]
|
||||
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
|
||||
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[FMAXNUM_IEEE]](<2 x s16>)
|
||||
; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
|
||||
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
|
||||
; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[TRUNC4]], [[C1]]
|
||||
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[TRUNC5]], [[C1]]
|
||||
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SELECT]](s16), [[SELECT1]](s16)
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](<2 x s16>)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fmaximum_v2f16
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<2 x s16>) = G_FMAXIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](<2 x s16>)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(<2 x s16>) = COPY $vgpr0
|
||||
%1:_(<2 x s16>) = COPY $vgpr1
|
||||
%2:_(<2 x s16>) = G_FMAXIMUM %0, %1
|
||||
$vgpr0 = COPY %2(<2 x s16>)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
---
|
||||
name: test_fmaximum_v2f32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||
|
||||
; GFX9-LABEL: name: test_fmaximum_v2f32
|
||||
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY2]]
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY2]]
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
|
||||
; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY1]], [[COPY3]]
|
||||
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY1]](s32), [[COPY3]]
|
||||
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FMAXNUM_IEEE1]], [[C]]
|
||||
; GFX9-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY4]](s32)
|
||||
; GFX9-NEXT: $vgpr1 = COPY [[COPY5]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
|
||||
;
|
||||
; GFX12-LABEL: name: test_fmaximum_v2f32
|
||||
; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY]], [[COPY2]]
|
||||
; GFX12-NEXT: [[FMAXIMUM1:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY1]], [[COPY3]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
|
||||
; GFX12-NEXT: $vgpr1 = COPY [[FMAXIMUM1]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(<2 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32)
|
||||
%3:_(s32) = COPY $vgpr2
|
||||
%4:_(s32) = COPY $vgpr3
|
||||
%5:_(<2 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32)
|
||||
%6:_(<2 x s32>) = G_FMAXIMUM %2, %5
|
||||
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(<2 x s32>)
|
||||
$vgpr0 = COPY %7(s32)
|
||||
$vgpr1 = COPY %8(s32)
|
||||
SI_RETURN implicit $vgpr0, implicit $vgpr1
|
||||
...
|
||||
---
|
||||
name: test_fmaximum_nsz_f32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_fmaximum_nsz_f32
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fmaximum_nsz_f32
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = nsz G_FMAXIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = nsz G_FMAXIMUM %0, %1
|
||||
$vgpr0 = COPY %2(s32)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
---
|
||||
name: test_fmaximum_nnan_f32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_fmaximum_nnan_f32
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FMAXNUM_IEEE]](s32)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fmaximum_nnan_f32
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = nnan G_FMAXIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = nnan G_FMAXIMUM %0, %1
|
||||
$vgpr0 = COPY %2(s32)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
|
||||
275
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
Normal file
275
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
Normal file
@ -0,0 +1,275 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
|
||||
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GFX12 %s
|
||||
|
||||
---
|
||||
name: test_fminimum_f16
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_fminimum_f16
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[TRUNC]], [[TRUNC1]]
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC1]]
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[SELECT]](s16)
|
||||
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fminimum_f16
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s16) = G_FMINIMUM [[TRUNC]], [[TRUNC1]]
|
||||
; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMINIMUM]](s16)
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s16) = G_TRUNC %0(s32)
|
||||
%2:_(s32) = COPY $vgpr1
|
||||
%3:_(s16) = G_TRUNC %2(s32)
|
||||
%4:_(s16) = G_FMINIMUM %1, %3
|
||||
%5:_(s32) = G_ANYEXT %4(s16)
|
||||
$vgpr0 = COPY %5(s32)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
---
|
||||
name: test_fminimum_f32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_fminimum_f32
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fminimum_f32
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = G_FMINIMUM %0, %1
|
||||
$vgpr0 = COPY %2(s32)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
---
|
||||
name: test_fminimum_f64
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
|
||||
; GFX9-LABEL: name: test_fminimum_f64
|
||||
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]]
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
|
||||
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0_vgpr1
|
||||
;
|
||||
; GFX12-LABEL: name: test_fminimum_f64
|
||||
; GFX12: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
|
||||
; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s64) = G_FMINIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[FMINIMUM]](s64)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0_vgpr1
|
||||
%0:_(s64) = COPY $vgpr0_vgpr1
|
||||
%1:_(s64) = COPY $vgpr2_vgpr3
|
||||
%2:_(s64) = G_FMINIMUM %0, %1
|
||||
$vgpr0_vgpr1 = COPY %2(s64)
|
||||
SI_RETURN implicit $vgpr0_vgpr1
|
||||
...
|
||||
---
|
||||
name: test_fminimum_v2f16
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_fminimum_v2f16
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
|
||||
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
|
||||
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
||||
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
|
||||
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
|
||||
; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
|
||||
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
|
||||
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
|
||||
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC2]]
|
||||
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC1]](s16), [[TRUNC3]]
|
||||
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
|
||||
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[FMINNUM_IEEE]](<2 x s16>)
|
||||
; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
|
||||
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
|
||||
; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[TRUNC4]], [[C1]]
|
||||
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[TRUNC5]], [[C1]]
|
||||
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SELECT]](s16), [[SELECT1]](s16)
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](<2 x s16>)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fminimum_v2f16
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(<2 x s16>) = G_FMINIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](<2 x s16>)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(<2 x s16>) = COPY $vgpr0
|
||||
%1:_(<2 x s16>) = COPY $vgpr1
|
||||
%2:_(<2 x s16>) = G_FMINIMUM %0, %1
|
||||
$vgpr0 = COPY %2(<2 x s16>)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
---
|
||||
name: test_fminimum_v2f32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||
|
||||
; GFX9-LABEL: name: test_fminimum_v2f32
|
||||
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY2]]
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY2]]
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
|
||||
; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY1]], [[COPY3]]
|
||||
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY1]](s32), [[COPY3]]
|
||||
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FMINNUM_IEEE1]], [[C]]
|
||||
; GFX9-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY4]](s32)
|
||||
; GFX9-NEXT: $vgpr1 = COPY [[COPY5]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
|
||||
;
|
||||
; GFX12-LABEL: name: test_fminimum_v2f32
|
||||
; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY]], [[COPY2]]
|
||||
; GFX12-NEXT: [[FMINIMUM1:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY1]], [[COPY3]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
|
||||
; GFX12-NEXT: $vgpr1 = COPY [[FMINIMUM1]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(<2 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32)
|
||||
%3:_(s32) = COPY $vgpr2
|
||||
%4:_(s32) = COPY $vgpr3
|
||||
%5:_(<2 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32)
|
||||
%6:_(<2 x s32>) = G_FMINIMUM %2, %5
|
||||
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(<2 x s32>)
|
||||
$vgpr0 = COPY %7(s32)
|
||||
$vgpr1 = COPY %8(s32)
|
||||
SI_RETURN implicit $vgpr0, implicit $vgpr1
|
||||
...
|
||||
---
|
||||
name: test_fminimum_nsz_f32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_fminimum_nsz_f32
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
|
||||
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
|
||||
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
|
||||
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fminimum_nsz_f32
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = nsz G_FMINIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = nsz G_FMINIMUM %0, %1
|
||||
$vgpr0 = COPY %2(s32)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
---
|
||||
name: test_fminimum_nnan_f32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_fminimum_nnan_f32
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
|
||||
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FMINNUM_IEEE]](s32)
|
||||
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
|
||||
; GFX9-NEXT: SI_RETURN implicit $vgpr0
|
||||
;
|
||||
; GFX12-LABEL: name: test_fminimum_nnan_f32
|
||||
; GFX12: liveins: $vgpr0, $vgpr1
|
||||
; GFX12-NEXT: {{ $}}
|
||||
; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = nnan G_FMINIMUM [[COPY]], [[COPY1]]
|
||||
; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
|
||||
; GFX12-NEXT: SI_RETURN implicit $vgpr0
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = nnan G_FMINIMUM %0, %1
|
||||
$vgpr0 = COPY %2(s32)
|
||||
SI_RETURN implicit $vgpr0
|
||||
...
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
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Reference in New Issue
Block a user