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[mips] MUL should clobber HI0 and LO0.

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I cannot think of a test case that reliably triggers this bug.

llvm-svn: 191109
This commit is contained in:
Akira Hatanaka 2013-09-20 21:22:28 +00:00
parent 4724963112
commit ff1fbda4cd
1 changed files with 1 additions and 0 deletions
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llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -878,6 +878,7 @@ def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
ADD_FM<0, 0x21>;
def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
ADD_FM<0, 0x23>;
let Defs = [HI0, LO0] in
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
ADD_FM<0x1c, 2>;
def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;