AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
Add a new constraint corresponding to the AV_* register classes for operands which can allocate AGPRs or VGPRs. This applies to load and stores on gfx90a+, and srcA / srcB for MFMA instructions. The error emitted on unsupported targets isn't ideal, it is produced by the register allocator without a rationale, but it is consistent with the existing errors. I mostly want this for writing allocation tests.
This commit is contained in:
Matt Arsenault
GitHub
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@ -5582,9 +5582,13 @@ AArch64:
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AMDGPU:
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- ``r``: A 32 or 64-bit integer register.
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- ``[0-9]v``: The 32-bit VGPR register, number 0-9.
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- ``[0-9]s``: The 32-bit SGPR register, number 0-9.
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- ``[0-9]a``: The 32-bit AGPR register, number 0-9.
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- ``s``: SGPR register or tuple
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- ``v``: VGPR register or tuple
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- ``a``: AGPR register or tuple. Only valid on gfx908+.
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- ``VA``: VGPR or AGPR register or tuple. Only valid on gfx90a+.
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- ``v[0-9]``: The 32-bit VGPR register, number 0-9.
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- ``s[0-9]``: The 32-bit SGPR register, number 0-9.
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- ``a[0-9]``: The 32-bit AGPR register, number 0-9.
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- ``I``: An integer inline constant in the range from -16 to 64.
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- ``J``: A 16-bit signed integer constant.
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- ``A``: An integer or a floating-point inline constant.
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@ -16906,13 +16906,26 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
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}
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break;
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}
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// We actually support i128, i16 and f16 as inline parameters
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// even if they are not reported as legal
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if (RC && (isTypeLegal(VT) || VT.SimpleTy == MVT::i128 ||
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VT.SimpleTy == MVT::i16 || VT.SimpleTy == MVT::f16))
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return std::pair(0U, RC);
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} else if (Constraint == "VA" && Subtarget->hasGFX90AInsts()) {
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const unsigned BitWidth = VT.getSizeInBits();
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switch (BitWidth) {
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case 16:
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RC = &AMDGPU::AV_32RegClass;
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break;
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default:
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RC = TRI->getVectorSuperClassForBitWidth(BitWidth);
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if (!RC)
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return std::pair(0U, nullptr);
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break;
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}
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}
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// We actually support i128, i16 and f16 as inline parameters
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// even if they are not reported as legal
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if (RC && (isTypeLegal(VT) || VT.SimpleTy == MVT::i128 ||
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VT.SimpleTy == MVT::i16 || VT.SimpleTy == MVT::f16))
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return std::pair(0U, RC);
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auto [Kind, Idx, NumRegs] = AMDGPU::parseAsmConstraintPhysReg(Constraint);
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if (Kind != '\0') {
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if (Kind == 'v') {
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@ -16997,6 +17010,9 @@ SITargetLowering::getConstraintType(StringRef Constraint) const {
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case 'a':
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return C_RegisterClass;
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}
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} else if (Constraint.size() == 2) {
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if (Constraint == "VA")
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return C_RegisterClass;
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}
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if (isImmConstraint(Constraint)) {
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return C_Other;
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27
llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint-err.ll
Normal file
27
llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint-err.ll
Normal file
@ -0,0 +1,27 @@
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; RUN: not llc -mtriple=amdgcn -mcpu=gfx90a -filetype=null %s 2>&1 | FileCheck %s
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; Make sure illegal type uses are correctly diagnosed
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; CHECK: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_i8(i8 %x) {
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call void asm sideeffect "; use $0", "^VA"(i8 %x)
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ret void
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}
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; CHECK: error: couldn't allocate output register for constraint 'VA'
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define i8 @def_A_i8() {
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%ret = call i8 asm sideeffect "; def $0", "=^VA"()
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ret i8 %ret
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}
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; CHECK: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_i1(i1 %x) {
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call void asm sideeffect "; use $0", "^VA"(i1 %x)
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ret void
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}
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; CHECK: error: couldn't allocate output register for constraint 'VA'
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define i1 @def_A_i1() {
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%ret = call i1 asm sideeffect "; def $0", "=^VA"()
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ret i1 %ret
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}
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217
llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint.ll
Normal file
217
llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint.ll
Normal file
@ -0,0 +1,217 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: not llc -mtriple=amdgcn -mcpu=gfx908 -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s
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; FIXME: Shouldn't emit and
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_i16(i16 %x) {
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; CHECK-LABEL: use_A_i16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(i16 %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_f16(half %x) {
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; CHECK-LABEL: use_A_f16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(half %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_bf16(bfloat %x) {
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; CHECK-LABEL: use_A_bf16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(bfloat %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_v2i16(<2 x i16> %x) {
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; CHECK-LABEL: use_A_v2i16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(<2 x i16> %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_v2f16(<2 x half> %x) {
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; CHECK-LABEL: use_A_v2f16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(<2 x half> %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_v2bf16(<2 x bfloat> %x) {
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; CHECK-LABEL: use_A_v2bf16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(<2 x bfloat> %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_i32(i32 %x) {
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; CHECK-LABEL: use_A_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(i32 %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_f32(float %x) {
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; CHECK-LABEL: use_A_f32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(float %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_i64(i64 %x) {
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; CHECK-LABEL: use_A_i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(i64 %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_f64(double %x) {
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; CHECK-LABEL: use_A_f64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(double %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_p1(ptr addrspace(1) %x) {
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; CHECK-LABEL: use_A_p1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(ptr addrspace(1) %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_v32i32(<32 x i32> %x) {
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; CHECK-LABEL: use_A_v32i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v[0:31]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(<32 x i32> %x)
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ret void
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}
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; ERR: error: couldn't allocate input reg for constraint 'VA'
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define void @use_A_v32f32(<32 x float> %x) {
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; CHECK-LABEL: use_A_v32f32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v[0:31]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "^VA"(<32 x float> %x)
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ret void
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}
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; ERR: error: couldn't allocate output register for constraint 'VA'
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define i16 @def_A_i16() {
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; CHECK-LABEL: def_A_i16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ret = call i16 asm sideeffect "; def $0", "=^VA"()
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ret i16 %ret
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}
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; ERR: error: couldn't allocate output register for constraint 'VA'
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define i32 @def_A_i32() {
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; CHECK-LABEL: def_A_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ret = call i32 asm sideeffect "; def $0", "=^VA"()
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ret i32 %ret
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}
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; ERR: error: couldn't allocate output register for constraint 'VA'
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define ptr addrspace(1) @def_A_p1() {
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; CHECK-LABEL: def_A_p1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ret = call ptr addrspace(1) asm sideeffect "; def $0", "=^VA"()
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ret ptr addrspace(1) %ret
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}
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