5 Commits

Author SHA1 Message Date
Jim Lin
22707fd4a5
[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)
The spec can be found at:

https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

The extension includes only two instructions: one for converting from
f32 to f16, and another for converting from f16 to f32.

This patch only implements MC support for XAndesBFHCvt.
2025-07-15 08:59:00 +08:00
Jim Lin
3f33e7ba5b
[RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only implements MC support for XAndesVSIntLoad.

---------

Co-authored-by: Lino Hsing-Yu Peng <linopeng@andestech.com>
2025-07-07 13:01:22 +08:00
Jim Lin
44bed1af0f [RISCV] Add negative pre-defined macro test for XAndesVBFHCvt 2025-07-03 09:06:01 +08:00
Jim Lin
8ddada41df
[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler. The instructions are similar to
`Zvfbfmin` and the only difference with `Zvfbfmin` is that
`XAndesVBFHCvt` doesn't have mask variant.
2025-06-18 09:17:46 +08:00
Jim Lin
94011efe30
[RISCV] Add pre-defined macro tests for Andes vendor extension. NFC. (#141172) 2025-06-03 11:32:28 +08:00