5 Commits

Author SHA1 Message Date
Alex Voicu
327c64cd6a
[HIP][SPIRV] Implicit new/delete should be cdecl on host (#152023)
Client apps can (and in the case of the MSVC STL do) set cdecl
explicitly on `new` / `delete` implementations. On the other hand, Clang
generates implicit decls with the target's default CC. This is
problematic for SPIR-V, since the default there is spir_function, which
is not compatible. Since we cannot change pre-existing headers /
implementations, this patch sets the CC to C for the implicit host-side
decls, when compiling for device, to prevent the conflict. This is fine
because the host-side overloards do not get emitted on device.
2025-08-08 12:31:28 -07:00
Juan Manuel Martinez Caamaño
d995b2ebdc
[Clang][AMDGPU] Accept builtins in lambda declarations (#135027)
`Sema::getCurFunctionDecl(AllowLambda = false)` returns a nullptr when
the lambda declaration is outside a function (for example, when
assigning a lambda to a static constexpr variable).

This triggered an assertion in
`SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall`.

Using `Sema::getCurFunctionDecl(AllowLambda = true)` returns the
declaration of the enclosing lambda.

Stumbled with this issue when refactoring some code in CK.
2025-04-11 19:11:46 +02:00
Vigneshwar Jayakumar
854d7301f9
[Clang/AMDGPU] Zero sized arrays not allowed in HIP device code. (#113470)
Added diagnosis to throw error when zero sized arrays are used in the
HIP device code. SWDEV-449592

---------

Co-authored-by: vigneshwar jayakumar <vigneshwar.jayakumar@amd.com>
2024-11-27 14:20:07 -06:00
Gang Chen
4ac0e7e400
[AMDGPU] Add a type for the named barrier (#113614) 2024-10-25 11:24:47 -07:00
Shilei Tian
ad599211a7
[Clang][AMDGPU] Add a new builtin type for buffer rsrc (#94830)
This patch adds a new builtin type for AMDGPU's buffer rsrc data type,
which is effectively an AS 8 pointer. This is needed because we'd like
to expose certain intrinsics to users via builtins which take buffer
rsrc as argument.
2024-06-18 20:46:53 -04:00