2 Commits

Author SHA1 Message Date
Kito Cheng
9b488ace17 [libunwind][RISC-V] Rewrite testcase with C as possible.
Fix #60472

The testcase is writen in all inline asm but it seems not well
maintained for the CFI directive, of cause we can fix that, but this
patch also contain another issue is it use s0 and s1 without
store/restore.

This patch proposed another way to testing that, use inline asm to
generate dummy def and use, so compiler will generate store/restore for
the vector register, and then generate the CFI directives.

Also check __riscv_vector as the testcase guard, because the testcase
will read vlenb which is only available when V or zve* extensions is
present.

Reviewed By: MaskRay, asb, #libunwind

Differential Revision: https://reviews.llvm.org/D145225
2023-03-15 17:30:16 +08:00
Sergey Kachkov
ca0b4d58ea [libunwind][RISCV] Support reading of VLENB CSR register
Support reading of VLENB (vector byte length) control register, that can be
required for correct unwinding of RVV objects on stack.

Differential Revision: https://reviews.llvm.org/D136264
2022-12-06 11:48:54 +03:00