191 Commits

Author SHA1 Message Date
Dmitry Nechitaev
14f33c6bc1
[llvm-objcopy][mach-o] Fix section finding logic for object files (#127604)
Fix section finding logic for object files.
As by product, make --update-section functional when the input is an object file.

This PR fixes #127495
2025-02-23 11:17:58 -08:00
Jonas Devlieghere
f71b83b359
[lldb] Add a release note for #127419 2025-02-17 18:29:24 -08:00
Nikita Popov
d8b2e432d6
[IR] Remove mul constant expression (#127046)
Remove support for the mul constant expression, which has previously
already been marked as undesirable. This removes the APIs to create mul
expressions and updates tests to stop using mul expressions.

Part of:
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179
2025-02-14 09:28:57 +01:00
Rahul Joshi
0f674cce82
[NFC][LLVM] Remove unused TargetIntrinsicInfo class (#126003)
Remove `TargetIntrinsicInfo` class as its practically unused (its pure
virtual with no subclasses) and its references in the code.
2025-02-10 14:56:30 -08:00
Adrian Vogelsgesang
8e6fa15bc3
[lldb-dap] Support column breakpoints (#125347)
This commit adds support for column breakpoints to lldb-dap

To do so, support for the `breakpointLocations` request was
added. To find all available breakpoint positions, we iterate over
the line table.

The `setBreakpoints` request already forwarded the column correctly to
`SBTarget::BreakpointCreateByLocation`. However, `SourceBreakpointMap`
did not keep track of multiple breakpoints in the same line. To do so,
the `SourceBreakpointMap` is now indexed by line+column instead of by
line only.

This was previously submitted as #113787, but got reverted due to
failures on ARM and macOS. This second attempt has less strict test
case expectations. Also, I added a release note.
2025-02-04 01:23:28 +01:00
Omair Javaid
2bffa5bf7a
[lldb][Windows] WoA HW Watchpoint support in LLDB (#108072)
This PR adds support for hardware watchpoints in LLDB for AArch64
Windows targets.

Windows does not provide an API to query the number of available
hardware watchpoints supported by underlying hardware platform.
Therefore, current implementation supports only a single hardware
watchpoint, which has been verified on Windows 11 using Microsoft
SQ2 and Snapdragon Elite X hardware.

LLDB test suite ninja check-lldb still fails watchpoint-related tests.
However, tests that do not require more than a single watchpoint
pass successfully when run individually.
2025-01-31 14:11:39 +05:00
Nikita Popov
29441e4f5f
[IR] Convert from nocapture to captures(none) (#123181)
This PR removes the old `nocapture` attribute, replacing it with the new
`captures` attribute introduced in #116990. This change is
intended to be essentially NFC, replacing existing uses of `nocapture`
with `captures(none)` without adding any new analysis capabilities.
Making use of non-`none` values is left for a followup.

Some notes:
* `nocapture` will be upgraded to `captures(none)` by the bitcode
   reader.
* `nocapture` will also be upgraded by the textual IR reader. This is to
   make it easier to use old IR files and somewhat reduce the test churn in
   this PR.
* Helper APIs like `doesNotCapture()` will check for `captures(none)`.
* MLIR import will convert `captures(none)` into an `llvm.nocapture`
   attribute. The representation in the LLVM IR dialect should be updated
   separately.
2025-01-29 16:56:47 +01:00
David Spickett
9ea64dd878
[lldb] Make Python >= 3.8 required for LLDB 21 (#124735)
As decided on
https://discourse.llvm.org/t/rfc-lets-document-and-enforce-a-minimum-python-version-for-lldb/82731.

LLDB 20 recommended `>= 3.8` but did not remove support for anything
earlier. Now we are in what will become LLDB 21, so I'm removing that
support and making
`>= 3.8` required.

See https://docs.python.org/3/c-api/apiabiversion.html#c.PY_VERSION_HEX
for the format of PY_VERSION_HEX.
2025-01-29 09:56:41 +00:00
Tom Stellard
3bd3e06f3f
Bump version to 21.0.0git (#124870)
Also clear the release notes.
2025-01-28 19:48:43 -08:00
gulfemsavrun
38902153fe
[PassBuilder] Add RelLookupTableConverterPass to LTO (#124053)
[PassBuilder] Add RelLookupTableConverterPass to LTO

This patch adds RelLookupTableConverterPass into the LTO
post-link optimization pass pipeline. This optimization
converts lookup tables to relative lookup tables to make
them PIC-friendly, which is already included in the non-LTO
pass pipeline. This patch adds this optimization to the
post-link optimization pipeline to discover more
opportunities in the LTO context.
2025-01-28 15:08:03 -08:00
David Spickett
8353aa2a53 [llvm][Docs] Add LLDB AArch64 GCS Release note
https://github.com/llvm/llvm-project/pull/124295 just
went in and that's the last piece of functionality.
2025-01-28 12:09:05 +00:00
David Spickett
b29bf3de05 [llvm][Docs] Re-order the LLDB release notes
To put generic changes first, moving into target specific changes
at the end.
2025-01-28 10:33:44 +00:00
Petr Hosek
b593110d89
[compiler-rt] Deprecate LLVM_ENABLE_PROJECTS in favor of LLVM_ENABLE_RUNTIMES (#124016)
We plan to make this a hard error in the LLVM 21 release.

Link #124012
2025-01-27 22:32:38 -08:00
Sam Elliott
d910fbcbd1 [RISCV][NFC] cR Constraint Release Note 2025-01-24 14:46:01 -08:00
Pavel Labath
0236cb6895
[lldb] Enable "frame diagnose" on linux (#123217)
.. by changing the signal stop reason format 🤦

The reason this did not work is because the code in
`StopInfo::GetCrashingDereference` was looking for the string "address="
to extract the address of the crash. Macos stop reason strings have the
form
```
  EXC_BAD_ACCESS (code=1, address=0xdead)
```
while on linux they look like:
```
  signal SIGSEGV: address not mapped to object (fault address: 0xdead)
```

Extracting the address from a string sounds like a bad idea, but I
suppose there's some value in using a consistent format across
platforms, so this patch changes the signal format to use the equals
sign as well. All of the diagnose tests pass except one, which appears
to fail due to something similar #115453 (disassembler reports
unrelocated call targets).

I've left the tests disabled on windows, as the stop reason reporting
code works very differently there, and I suspect it won't work out of
the box. If I'm wrong -- the XFAIL will let us know.
2025-01-23 13:04:36 +01:00
quic_hchandel
163935a48d
[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)
This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-23 10:14:25 +05:30
Weining Lu
d80b814c01 [LoongArch] Summary llvm20 release notes 2025-01-23 12:38:04 +08:00
Alexey Merzlyakov
ef37c3dd03
[llvm][Docs] Release note for LLDB optionally disabled regsets for RV64 (#123363)
This PR adds the release note point for LLDB 20, discussed in
https://github.com/llvm/llvm-project/pull/104547#issuecomment-2587479877
for the same ticket

---------

Co-authored-by: David Spickett <david.spickett@linaro.org>
2025-01-22 09:30:13 +00:00
dlav-sc
0d24130008
[llvm][Docs] Add lldb user expressions related release notes (#123772) 2025-01-22 12:25:44 +03:00
Michal Paszkowski
cda81b1ec9
[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS (reapply) (#123733)
This commit promotes the SPIR-V backend from experimental to official
status. As a result, SPIR-V will be built by default, simplifying
integration and increasing accessibility for downstream projects.

Discussion and RFC on Discourse:
https://discourse.llvm.org/t/rfc-promoting-spir-v-to-an-official-target/83614

The PR reapplies the original patch
https://github.com/llvm/llvm-project/pull/119653 and consecutive
https://github.com/llvm/llvm-project/pull/123654, reverted due to
buildbot failures.
2025-01-21 12:39:03 +01:00
Michal Paszkowski
3f0ac4653b
Revert "[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS (reapply)" (#123674)
Reverts llvm/llvm-project#123654 due to buildbot issue
2025-01-20 15:16:43 -08:00
Michal Paszkowski
f427fef092
[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS (reapply) (#123654)
This commit promotes the SPIR-V backend from experimental to official
status. As a result, SPIR-V will be built by default, simplifying
integration and increasing accessibility for downstream projects.

Discussion and RFC on Discourse:
https://discourse.llvm.org/t/rfc-promoting-spir-v-to-an-official-target/83614

The PR reapplies the original patch
https://github.com/llvm/llvm-project/pull/119653, reverted due to
buildbot failures.
2025-01-20 14:57:41 -08:00
Michal Paszkowski
5af7905302
Revert "[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS" (#123532)
Reverts llvm/llvm-project#119653
2025-01-20 00:33:14 +01:00
Michal Paszkowski
c46df85380
[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS (#119653)
This commit promotes the SPIR-V backend from experimental to official
status. As a result, SPIR-V will be built by default, simplifying
integration and increasing accessibility for downstream projects.

Discussion and RFC on Discourse:
https://discourse.llvm.org/t/rfc-promoting-spir-v-to-an-official-target/83614
2025-01-20 00:02:46 +01:00
Pavel Labath
f711aa9e5d
[llvm][Docs] Add release note about LLDB core file improvements (#123062) 2025-01-16 08:29:40 +01:00
Pavel Labath
7900769985
[llvm][Docs] Add a release note about the lldb DWARF indexing speedup (#122870)
The figure includes works that's already committed. In does not include
the WIP/RFC proposal in
https://discourse.llvm.org/t/rfc-speeding-up-dwarf-indexing-again/83979.
2025-01-14 15:54:19 +01:00
David Spickett
cfd7e024c6 [llvm][Docs] Add release note for lldb-server port mapping changes 2025-01-14 10:01:08 +00:00
David Spickett
04733fac10 [llvm][Docs] Formatting changes to LLDB release notes 2025-01-14 10:01:07 +00:00
Jacob Lalonde
df1a84d2ed
[llvm][Docs] Add Minidump related LLDB release notes (#122759)
Add some release notes for the Minidump work I did over the last few
months.
2025-01-14 09:35:41 +00:00
jimingham
386dec2be9
Update ReleaseNotes.md
Mentioned native command definitions and support for breaking on inlined call-sites.
2025-01-13 14:43:19 -08:00
David Spickett
3d507a8905
[llvm][Docs] Add new LLDB Python guidance to release notes (#122719)
As decided in
https://discourse.llvm.org/t/rfc-lets-document-and-enforce-a-minimum-python-version-for-lldb/82731
and implemented by https://github.com/llvm/llvm-project/pull/114807.
2025-01-13 16:31:01 +00:00
quic_hchandel
171d3edd05
[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)
This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-13 16:36:05 +05:30
Heejin Ahn
a8e1135baa
[WebAssembly] Add -wasm-use-legacy-eh option (#122158)
This replaces the existing `-wasm-enable-exnref` with
`-wasm-use-legacy-eh` option, in an effort to make the new standardized
exnref proposal the 'default' state and the legacy proposal needs to be
separately enabled an option. But given that most users haven't switched
to the new proposal and major web browsers haven't turned it on by
default, this `-wasm-use-legacy-eh` is turned on by default, so nothing
will change for now for the functionality perspective.

This also removes the restriction that `-wasm-enable-exnref` be only
used with `-wasm-enable-eh` because this option is enabled by default.
This option does not have any effect when `-wasm-enable-eh` is not used.
2025-01-09 22:36:10 -08:00
Heejin Ahn
876841b0e2
[WebAssembly] Format WebAssembly ReleaseNote entries (#122203) 2025-01-09 11:37:40 -08:00
Craig Topper
5d03235c73
[RISCV] Add -mcpu=sifive-p550. (#122164)
This is the CPU in SiFive's HiFive Premier P550 development board.

Scheduler model will come in a later patch.
2025-01-08 21:02:46 -08:00
quic_hchandel
737d6ca44d
[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-07 08:25:00 +05:30
Shao-Ce SUN
2fae5bdea7
[RISCV] Add support of Sdext,Sdtrig extentions (#120936)
`Sdext` and `Sdtrig` are RISC-V extensions related to debugging.

The full specification can be found at

https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf
2025-01-03 17:25:42 +08:00
Sudharsan Veeravalli
532a2691bc
[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)
This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
2025-01-03 06:33:27 +05:30
quic_hchandel
1557eeda73
[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)
This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2024-12-29 11:14:12 +05:30
Kinoshita Kotaro
88d04be815
[AArch64][docs] Add release notes for FUJITSU-MONAKA support (#120684)
Adds release notes for the FUJITSU-MONAKA support introduced in PR #118432.
These notes were missing from the original PR.
2024-12-25 10:59:59 +09:00
Richard Dzenis
334a5766d7
[llvm-objcopy] Add support of symbol modification flags for MachO (#120895)
This patch adds support of the following llvm-objcopy flags for MachO:

- `--globalize-symbol`, `--globalize-symbols`,
- `--keep-global-symbol`, `-G`, `--keep-global-symbols`,
- `--localize-symbol`, `-L`, `--localize-symbols`,
- `--skip-symbol`, `--skip-symbols`.

Code in `updateAndRemoveSymbols` for MachO
is kept similar to its version for ELF.

Fixes #120894
2024-12-24 16:05:10 +02:00
Richard Dzenis
944b6f8523 [llvm][NFC] Fix typo in ReleaseNotes 2024-12-23 13:37:00 +02:00
Djordje Todorovic
52e9f2c52c
[RISCV] Add MIPS P8700 processor (#119882)
The P8700 is a high-performance processor from MIPS designed to meet the
demands of modern workloads, offering exceptional scalability and
efficiency. It builds on MIPS's established architectural strengths
while introducing enhancements that set it apart. For more details, you
can check out the official product page here:
https://mips.com/products/hardware/p8700/.

Scheduling model will be added in a separate commit/PR.
2024-12-13 20:54:25 +01:00
Sudharsan Veeravalli
668d9688ac
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
2024-12-14 00:06:58 +05:30
quic_hchandel
0614c601b4
[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)
The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2024-12-12 11:12:09 +05:30
Feng Zou
94c6dd62fa
[docs] Update release notes for APX relocation types (#118575) 2024-12-07 21:27:10 +08:00
Chandler Carruth
28bba0d717
Bump minimum MSVC version by one dot release to VS 2019 16.8 (#118833)
This is a small change, but unblocks using longer string literals in
LLVM's source code, and hopefully isn't disruptive.

Discussed in an RFC here:
https://discourse.llvm.org/t/rfc-raising-minimum-msvc-version-by-one-dot-release/
2024-12-06 01:48:02 -08:00
John Brawn
ecbe4d1e36
[IR] Allow fast math flags on fptrunc and fpext (#115894)
This consists of:
 * Make these instructions part of FPMathOperator.
* Adjust bitcode/ir readers/writers to expect fast math flags on these
instructions.
 * Make IRBuilder set the fast math flags on these instructions.
 * Update langref and release notes.
* Update a bunch of tests. Some of these are due to InstCombineCasts
incorrectly adding fast math flags to fptrunc, which will be fixed in a
later patch.
2024-12-04 10:53:04 +00:00
Shilei Tian
68bcba6d7a Revert "[AMDGPU] Use COV6 by default (#118515)"
This reverts commit 410cbe3cf28913cca2fc61b3437306b841d08172 because some
buildbots are not ready yet.
2024-12-03 20:17:06 -05:00
Shilei Tian
410cbe3cf2
[AMDGPU] Use COV6 by default (#118515) 2024-12-03 19:38:35 -05:00