55 Commits

Author SHA1 Message Date
Jared Wyles
2ccf7ed277
[JITLink] Switch to SymbolStringPtr for Symbol names (#115796)
Use SymbolStringPtr for Symbol names in LinkGraph. This reduces string interning
on the boundary between JITLink and ORC, and allows pointer comparisons (rather
than string comparisons) between Symbol names. This should improve the
performance and readability of code that bridges between JITLink and ORC (e.g.
ObjectLinkingLayer and ObjectLinkingLayer::Plugins).

To enable use of SymbolStringPtr a std::shared_ptr<SymbolStringPool> is added to
LinkGraph and threaded through to its construction sites in LLVM and Bolt. All
LinkGraphs that are to have symbol names compared by pointer equality must point
to the same SymbolStringPool instance, which in ORC sessions should be the pool
attached to the ExecutionSession.
---------

Co-authored-by: Lang Hames <lhames@gmail.com>
2024-12-06 10:22:09 +11:00
Jonas Hahnfeld
78f39dc70c
[JITLink][RISCV] Use hashmap to find PCREL_HI20 edge (#78849)
As noted in issues #68594 and #73935, `JITLink/RISCV/ELF_ehframe.s`
fails with libstdc++'s expensive checks because `getRISCVPCRelHi20`
calls `std::equal_range` on the edges which may not be ordered by their
offset. Instead let `ELFJITLinker_riscv` build a hashmap of all edges
with type `R_RISCV_PCREL_HI20` that can be looked up in constant time.

Closes #73935
2024-02-12 19:45:52 +01:00
Craig Topper
8c37e3e64b
[RISCV] Only set Zca flag for EF_RISCV_RVC in ELFObjectFileBase::getRISCVFeatures(). (#80928)
This code appears to be a hack to set the features to include compressed
instructions if the ELF EFLAGS flags bit is present, but the ELF
attribute for the ISA string is no present or not accurate.

We can't remove the hack because llvm-mc doesn't create ELF attributes
by default so a lot of tests fail to disassembler properly. Using clang
as the assembler does set the attributes.

This patch changes the hack to only set Zca since that is the minimum
implied by the flag. Setting anything else potentially conflicts with
the ISA string containing Zcmp or Zcmt.

JITLink also needs to be updated to recognize Zca in addition to C.
2024-02-07 08:23:57 -08:00
Jonas Hahnfeld
4f6757ce4b
[JITLink][RISCV] Implement eh_frame handling (#68253)
This requires adding a `NegDelta32` edge kind that cannot be mapped to
existing relocations.

Co-authored-by: Job Noorman <jnoorman@igalia.com>
2023-10-28 11:30:43 +02:00
Kazu Hirata
8a7f4eeb60 [llvm] Use llvm::is_contained (NFC) 2023-09-22 17:09:27 -07:00
Job Noorman
67f7efbbbb [JITLink][RISCV] Fix use-after-free in relax
Finalization of relaxation calls `finalizeBlockRelax` for every block in
the graph. This function, however, would iterate over //all// blocks in
the graph to remove `AlignRelaxable` edges. Since pointers to those
edges would still be stored in `RelaxEdges`, this caused a
use-after-free for graphs with multiple blocks.

This patch fixes this by only iterating over the edges of the current
block in `finalizeBlockRelax`.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D154844
2023-07-13 09:02:19 +02:00
Job Noorman
1e60ab0fbe [JITLink][RISCV] Move relax to PostAllocationPasses
`JITLinkContext` is notified (using `notifyResolved`) of the final
symbol addresses after allocating memory and running the post-allocation
passes. However, linker relaxation, which can cause symbol addresses to
change, was run during the pre-fixup passes. This causes users of
JITLink (e.g., ORC) to pick-up wrong symbol addresses when linker
relaxation was enabled.

This patch fixes this by running relaxation during the post-allocation
passes.

Fixes #63671

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D154501
2023-07-06 09:35:17 +02:00
Job Noorman
52b88457ba [JITLink] Use SubtargetFeatures to store features in LinkGraph
D149522 introduced target features to LinkGraph. However, to avoid a
public dependency on MC, the features were stored in a std::vector
instead of using SubtargetFeatures directly.

Since SubtargetFeatures was moved from MC to TargetParser (D150549), we
can now use it directly to store the features. This patch implements
that and removes the (private) dependency on MC.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D153749
2023-06-27 09:34:46 +02:00
Job Noorman
794970988e [JITLink][RISCV] Adjust offsets of non-relaxable edges
The relaxation algorithm used to only update offsets of relaxable edges.
This caused non-relaxable edges that appear after a relaxed instruction
to have an incorrect offset and be applied at the wrong location. This
patch fixes this by updating the offsets of all edges.

Note that this bug was caused by an incorrect translation of LLD's
relaxation algorithm. LLD always uses all edges during relaxation while
I decided to filter-out relaxable edges to prevent having to iterate
non-relaxable edges at each step. However, this had the side-effect of
only updating offsets of relaxable edges. This patch leaves the
filtering of relaxable edges as-is but iterates all edges when updating
offsets.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D153515
2023-06-26 09:41:20 +02:00
Job Noorman
de5198b00d [JITLink][RISCV] Expose relaxation pass publicly
This is useful for contexts where shouldAddDefaultTargetPasses returns
false but that still want to perform relaxation.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D153538
2023-06-26 09:41:20 +02:00
Job Noorman
f4bb62e85c [JITLink][RISCV] Support relaxable edges without relaxation pass
Relaxable edges are created unconditionally, even when the relaxation
pass will not run. However, they were not recognized by applyFixup
causing them to not be applied.

To support configurations without the relaxation pass, this patch adds
these relaxable edges to applyFixup:
- CallRelaxable: Can be treated as R_RISCV_CALL
- AlignRelaxable: Can simply be ignored

An alternative could be to unconditionally run the relaxation pass, even
in contexts where shouldAddDefaultTargetPasses returns false. However, I
could imagine there being use cases for disabling relaxation which
wouldn't be possible anymore then.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D153541
2023-06-26 09:41:20 +02:00
Job Noorman
bcd1296a1a [JITLink][RISCV] Consider relaxable call edges for PLT edges
For linker relaxation (D149526), a new edge kind (`CallRelaxable`) was
introduced. However, this new kind was not taken into account by
`PerGraphGOTAndPLTStubsBuilder_ELF_riscv`. This patch fixes this.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D150957
2023-05-22 10:41:32 +02:00
Job Noorman
310473c536 [JITLink][RISCV] Implement linker relaxation
This patch is essentially an adaption of LLD's algorithm to JITLink.
Currently, only relaxing R_RISCV_CALL(_PLT) and R_RISCV_ALIGN is
implemented, other relocations can follow later.

From a high level, the algorithm works as follows. In the first phase
(relaxBlock), we iteratively try to relax all instructions that have a
R_RISCV_RELAX relocation:
- If, based on the current symbol values, an instruction sequence can be
  relaxed (i.e., replaced by a shorter instruction), we record how many
  bytes would be removed, the new instruction (Writes), and the new
  relocation type (EdgeKinds).
- We keep track of the total number of bytes that got removed up to each
  relocation in the RelocDeltas array. This is the cumulative sum of the
  number of bytes removed for each relocation.
- Symbol values and sizes are updated based on the number of removed
  bytes.
- If for any relocation, the current RelocDeltas value doesn't match the
  one from the previous iteration, something changed and we need to run
  another iteration as some symbols might now have different values.

In the second phase (finalizeBlockRelax), all code is moved based on
RelocDeltas, the relaxed instructions are rewritten using Writes, and
R_RISCV_ALIGN is handled (moving instructions to ensure alignment and
inserting the correct NOP-sequence if needed). Finally, edge kinds and
offsets are updated and all R_RISCV_RELAX and R_RISCV_ALIGN edges are
removed (they are not needed anymore for the fixup linking stage).

Linker relaxation is implemented as a pass and added to PreFixupPasses
in the default configuration on RISC-V.

Since linker relaxation removes instructions, the memory for blocks
should ideally be reallocated. However, I believe this is currently not
possible in JITLink. Therefore, relaxation directly modifies the memory
of blocks, reducing the number of instructions but not the size of
blocks. I'm not very familiar with JITLink's memory allocators so I
might be overlooking something here, though.

Note on testing: some of the tests rely on the debug output of
llvm-jitlink. The main reason for this is the verification of symbol
sizes (which may change due to relaxation). I don't believe this can be
done using jitlink-check checks alone.

Note that there is a slightly unrelated change that makes
Symbol::setOffset public to be able to update symbol offsets during
relaxation.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D149526
2023-05-17 11:35:19 +02:00
Job Noorman
348d0a6bf6 [JITLink] Add target features to LinkGraph
This patch adds SubtargetFeatures to LinkGraph. Similar to Triple, some
targets might use this information while linking.

One example, and the reason this patch was written, is linker relaxation
on RISC-V: different relaxations are possible depending on if the C
extension is enabled.

Note that the features are stored as `std::vector<std::string>` to prevent a
public dependency on MC. There is still a private dependency to be able to
convert SubtargetFeatures to a vector.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D149522
2023-05-17 11:35:19 +02:00
Job Noorman
26ee894770 [JITLink][RISCV] Only generate PLT entries for external symbols
R_RISCV_CALL has been deprecated. [1] Both GCC and LLVM seem to not
generate it anymore and always use R_RISCV_CALL_PLT (even for calls that
do not need a PLT entry). Generating PLT entries based on relocation
type is not recommended and a better heuristic is to only generate them
when the target symbol is preemptable [2]. This patch implements this by
only generating PLT entries for undefined symbols.

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/340
[2] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/98

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D149525
2023-05-08 10:31:33 +02:00
Job Noorman
4752787cc3 [JITLink][RISCV] Handle R_RISCV_CALL_PLT fixups
In the default link configuration, PLT stubs are created automatically
for R_RISCV_CALL_PLT relocations and the relocation itself is
transformed to R_RISCV_CALL (PerGraphGOTAndPLTStubsBuilder_ELF_riscv).
Only the latter is later handled when applying fixups and the former is
simply ignored.

This patch proposes to handle R_RISCV_CALL_PLT anyway when applying
fixups to support custom configurations that do not need automatic PLT
creation. An example of this is BOLT where PLT entries from the input
binary are reused (D147544).

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D148238
2023-04-14 09:11:19 +02:00
Job Noorman
6a14a56aaf [JITLink][RISCV] ADD/SUB relocs: read value from working memory
The various ADD/SUB relocations work by reading the current value the
relocation points to, transforming it, and then writing it back to
memory. While the current implementation writes the value back to
working memory, it reads the current value from the execution address of
the relocation. This causes at least wrong results, but often crashes,
when the addresses of working memory are not equal to execution
addresses. This patch fixes this by reading the current value from
working memory.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D147693
2023-04-07 09:47:49 +02:00
Stefan Gränitz
59b8db1db8 [JITLink] Drop const qualifier from argument to ELFLinkGraphBuilder's ctors (NFC)
These values are moved into the base class constructors, so the `const` doesn't make any sense. Turns out, I accidentally introduced it myself with 2ed91da0f1f3 and since than it spread by copy/paste.
2023-02-15 10:54:51 +01:00
Jonas Hahnfeld
c8d43dca23 [JITLink][RISCV] Add R_RISCV_RVC_BRANCH and R_RISCV_RVC_JUMP
These are the compressed equivalents of the relocations R_RISCV_BRANCH
and R_RISCV_JAL with slightly more complex immediate handling.

Differential Revision: https://reviews.llvm.org/D140827
2023-01-04 13:51:15 +01:00
Jonas Hahnfeld
850adc1ddc [JITLink][RISCV] Homogenize immediate handling
Name the variables based on which part of the immediate value is
extracted, as it was already done for R_RISCV_JAL. This makes it
much easier to compare the logic with the spec.

Differential Revision: https://reviews.llvm.org/D140820
2023-01-03 17:18:39 +01:00
Jonas Hahnfeld
e7d432fd67 [JITLink][RISCV] Improve R_RISCV_JAL
Only take the lower 12 bits of RawInstr.

Differential Revision: https://reviews.llvm.org/D140820
2023-01-03 17:18:39 +01:00
Jonas Hahnfeld
6f539de735 [JITLink][RISCV] Order EdgeKind_riscv the same way as relocations
There were basically four different orderings: one defined by the
relocations, one by the enum definition of EdgeKind_riscv, one for
mapping the enum values to their names, and one when mapping the
relocations to edge kinds and finally processing them. Chose the
ordering defined by the relocations in the riscv-elf-psabi-doc as
the canonical one.

Differential Revision: https://reviews.llvm.org/D140802
2023-01-02 14:49:47 +01:00
luxufan
31000211e0 [JITLink][RISCV] Fix incorrectly use of uint32_t 2023-01-02 13:48:39 +08:00
Dmitry Kurtaev
a2c9f12dd6 [RISCV][JitLink] Propagate error from Expected<T> result during R_RISCV_PCREL_HI20 parsing
related issue: https://github.com/llvm/llvm-project/issues/59139

Differential Revision: https://reviews.llvm.org/D138781
2022-12-07 08:26:38 -08:00
luxufan
f8979512ea [JITLink][RISCV] Add R_RISCV_LO12_S relocation support
Fixes: https://github.com/llvm/llvm-project/issues/58979

Reviewed By: Hahnfeld

Differential Revision: https://reviews.llvm.org/D138030
2022-11-16 19:50:18 +08:00
Kshitij Jain
2a3b257a93 [JITLink][i386] Adds absolute and pc relative relocation support for ELF/i386.
This commit adds support for 32 bit absolute and pc relative relocations in
ELF/i386 objects, along with simple regression tests.

Reviewed By: sgraenitz, lhames

Differential Revision: https://reviews.llvm.org/D135523
2022-10-30 17:35:41 -07:00
Lang Hames
d3d9f7caf9 [ORC][JITLink] Move MemoryFlags.h (MemProt, AllocGroup,...) from JITLink to ORC.
Moving these types to OrcShared eliminates the need for the separate
WireProtectionFlags type.
2022-10-03 19:35:34 -07:00
Jonas Hahnfeld
f5b5398ebf [JITLink][RISCV] Ignore R_RISCV_RELAX and check R_RISCV_ALIGN
It is fine to not implement and ignore linker relaxation for now, but
we need to check the alignment. Luckily, an alignment of only 2 bytes
is the most common case when interpreting C++ code in clang-repl, and
already guaranteed by the length of compressed instructions.

Differential Revision: https://reviews.llvm.org/D129159
2022-07-06 18:09:19 +02:00
Sunho Kim
9fc0aa45e3 [JITLink][ELF] Log enum name of unsupported relocation type.
Logs enum name of unsupported relocation type. This also changes elf/x86 to use common util function (getELFRelocationTypeName) inside llvm object module.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D127715
2022-06-15 23:26:29 +09:00
Simon Pilgrim
1df20fa8f5 [JITLink] Fix -Wparentheses warning in R_RISCV_SUB6 case.
Perform the mask inside parentheses before applying the offset
2022-03-15 14:13:28 +00:00
fourdim
16dc90cbe7 [JITLink][RISCV] Refactor range checking and alignment checking
This patch refactors the range checking function to make it compatible with all relocation types and supports range checking for R_RISCV_BRANCH. Moreover, it refactors the alignment check functions.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D117946
2022-03-09 22:13:57 +08:00
luxufan
3362f54d08 [JITLink] Add R_RISCV_SUB6 relocation
Add R_RISCV_SUB6 relocation

Differential Revision: https://reviews.llvm.org/D120001
2022-03-01 01:45:03 +08:00
fourdim
1ece3eeeb7 [JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation.
This patch supports the R_RISCV_JAL relocation.
Moreover, it will fix the extractBits function's behavior as it extracts Size + 1 bits.
In the test ELF_jal.s:
Before:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 480
```
After:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 224
```

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D117975
2022-02-18 14:07:28 +08:00
fourdim
051f7cdcd2 Revert "[JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation."
This reverts commit 3af7bbca4a0ef64de64b8bb38d3b167673ec60f0.
2022-02-17 23:40:32 +08:00
fourdim
3af7bbca4a [JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation.
This patch supports the R_RISCV_JAL relocation.
Moreover, it will fix the extractBits function's behavior as it extracts Size + 1 bits.
In the test ELF_jal.s:
Before:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 480
```
After:
```
Hi: 4294836480
extractBits(Hi, 12, 8): 224
```

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D117975
2022-02-17 23:03:36 +08:00
luxufan
9920943ea2 [JITLink] Fix the incorrect relocation behavior for R_RISCV_BRANCH
In D116573, the relocation behavior of R_RISCV_BRANCH didn't consider that branch instruction like 'bge' has a branch target address which is given as a PC-relative offset, sign-extend and multiplied by 2.
Although the target address is a 12-bits number, acctually its range is [-4096, 4094].

This patch fix it.

Differential Revision: https://reviews.llvm.org/D118151
2022-02-07 14:34:19 +08:00
fourdim
f7d4cafe5a [JITLink][RISCV] Support R_RISCV_SET* and R_RISCV_32_PCREL relocations
This patch supports R_RISCV_SET* and R_RISCV_32_PCREL relocations in JITLink.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D117082
2022-01-22 03:34:51 +08:00
luxufan
fdb6578514 Revert "[JITLink] Add anonymous symbols in LinkGraph for unnamed temporary symbols"
This reverts commit de872382951572b70dfaefe8d77eb98d15586115.

Buildbot check error
2022-01-22 17:26:54 +08:00
luxufan
de87238295 [JITLink] Add anonymous symbols in LinkGraph for unnamed temporary symbols
In RISCV, temporary symbols will be used to generate dwarf, eh_frame sections..., and will be placed in object code's symbol table. However, LLVM does not use names on these temporary symbols. This patch add anonymous symbols in LinkGraph for these temporary symbols.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D116475
2022-01-22 16:47:39 +08:00
luxufan
dc18c5fa97 [JITLink] Add RISCV label subtraction and addition relocations
This patch add RISCV label subtraction and addition relocations in JITLink

Differential Revision: https://reviews.llvm.org/D116794
2022-01-19 22:12:56 +08:00
Steven Wu
091e364866 [JITLink][ELF] Support duplicated section names from object file
ELF object files can contain duplicated sections (thus section symbols
as well), espeically when comdats/section groups are present. This patch
adds support for generating LinkGraph from object files that have
duplicated section names. This is the first step to properly model
comdats/section groups.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D114753
2022-01-18 08:38:28 -08:00
fourdim
0c6f762622 [jitlink] add R_RISCV_BRANCH to jitlink
This patch supported the R_RISCV_BRANCH relocation.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D116573
2022-01-15 03:36:58 +08:00
luxufan
0ef5aa69e7 [JITLink] Add fixup value range check
This patch makes jitlink to report an out of range error when the fixup value out of range

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D107328
2022-01-13 16:32:49 +08:00
Lang Hames
118e953b18 Re-apply "[JITLink] Update JITLink to use ExecutorAddr rather... " with fixes.
This re-applies 133f86e95492b2a00b944e070878424cfa73f87c, which was reverted in
c5965a411c635106a47738b8d2e24db822b7416f while I investigated bot failures.

The original failure contained an arithmetic conversion think-o (on line 419 of
EHFrameSupport.cpp) that could cause failures on 32-bit platforms. The issue
should be fixed in this patch.
2022-01-06 17:22:21 +11:00
Lang Hames
c5965a411c Revert "[JITLink] Update JITLink to use ExecutorAddr rather than..."
This reverts commit 133f86e95492b2a00b944e070878424cfa73f87c while I investigate
the bot failures at https://lab.llvm.org/buildbot#builders/186/builds/3370.
2022-01-06 15:20:21 +11:00
Lang Hames
133f86e954 [JITLink] Update JITLink to use ExecutorAddr rather than JITTargetAddress.
ExecutorAddr is the preferred representation for executor process addresses now.
2022-01-06 13:48:12 +11:00
luxufan
43c5fffcef Revert "[JITLink] Add fixup value range check"
This reverts commit 17af06ba8005d6d14b0ac79ece01ecb028de9f90.
2022-01-05 00:04:09 +08:00
luxufan
17af06ba80 [JITLink] Add fixup value range check
This patch makes jitlink to report an out of range error when the fixup value out of range

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D107328
2022-01-04 22:45:15 +08:00
luxufan
95b74d4db0 [JITLink] Improve extractBits function
Address the advice proposed at patch D105429 . Use [Low, Low+size) to represent bits.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D107250
2022-01-04 20:05:50 +08:00
Lang Hames
962a2479b5 Re-apply e50aea58d59, "Major JITLinkMemoryManager refactor". with fixes.
Adds explicit narrowing casts to JITLinkMemoryManager.cpp.

Honors -slab-address option in llvm-jitlink.cpp, which was accidentally
dropped in the refactor.

This effectively reverts commit 6641d29b70993bce6dbd7e0e0f1040753d38842f.
2021-10-11 21:39:00 -07:00