This is a series of patches (4/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.
This patch:
* removes .txt tests whose .s tests have functions
* makes the .s tests have a roundabout run line to test both encoding
and assembly
See also #146328, #146329 and #146330.
Co-authored-by: Virginia Cangelosi <virginia.cangelosi@arm.com>
This is a series of patches (3/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.
This patch:
* removes .txt tests which have multiple feature dependencies
* makes the .s tests have a roundabout run line to test both encoding
and assembly
* creates diagnostic tests when needed
See also #146328, #146329 and #146331.
Co-authored-by: Virginia Cangelosi <virginia.cangelosi@arm.com>
This is a series of patches (2/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.
This patch:
* removes .txt tests which have only one feature required
* makes the .s tests have a roundabout run line to test both encoding
and assembly
* creates diagnostic tests when needed
* fixes naming convention of tests
See also #146328, #146330 and #146331.
Co-authored-by: Virginia Cangelosi <virginia.cangelosi@arm.com>
This is a series of patches (1/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.
This patch:
* unifies errorless .s and .txt tests into a single file
* remove .txt tests which don't have feature requirements
* makes the .s tests have a roundabout run line to test both encoding
and assembly
See also #146329, #146330 and #146331.
---------
Co-authored-by: Virginia Cangelosi <virginia.cangelosi@arm.com>
This implements very basic support for RISC-V mapping symbols in
llvm-objdump, sharing the implementation with how Arm/AArch64/CSKY
implement this feature.
This only supports the `$x` (instruction) and `$d` (data) mapping
symbols for RISC-V, and not the version of `$x` which includes an
architecture string suffix.
The current disassembly of `ldt{add,set,clr}` instructions when using
`xzr/wzr` is incorrect. The Armv9.6-A Memory Systems specification says:
```
For each of LDT{ADD|SET|CLR}{L}, there is the corresponding STT{ADD|SET|CLR}{L}
alias, for the case where the register selected by the Rt field is XZR or WZR
```
and:
```
LDT{ADD|SET|CLR}{A}{L} is equivalent to LD{ADD|SET|CLR}{A}{L} except that: <..conditions..>
```
The Arm ARM specifies the preferred form of disassembly for these
aliases:
```
STADD <Xs>, [<Xn|SP>]
is equivalent to
LDADD <Xs>, XZR, [<Xn|SP>]
and is always the preferred disassembly.
```
(ref: DDI 0487L.b C6-2317)
This means that `sttadd` is the preferred disassembly for `ldtadd w0,
wzr, [x2]` when Rt is `xzr` or `wzr`.
This change also aligns llvm disassembly with GNU binutils, as shown by
the following examples:
llvm before this change:
```
% cat test.s
stadd w0, [sp]
sttadd w0, [sp]
ldadd w0, wzr, [sp]
ldtadd w0, wzr, [sp]
% llvm-mc-20 -triple aarch64 -mattr=+lse,+lsui test.s
stadd w0, [sp]
ldtadd w0, wzr, [sp]
stadd w0, [sp]
ldtadd w0, wzr, [sp]
```
llvm after this change:
```
% llvm-mc -triple aarch64 -mattr=+lse,+lsui test.s
stadd w0, [sp]
sttadd w0, [sp]
stadd w0, [sp]
sttadd w0, [sp]
```
GCC-15 test:
```
% gas test.s -march=armv8-a+lsui+lse -o test.o
% objdump -dr test.o
0: b82003ff stadd w0, [sp]
4: 192007ff sttadd w0, [sp]
8: b82003ff stadd w0, [sp]
c: 192007ff sttadd w0, [sp]
```
Many thanks to Ezra Sitorus and Alice Carlotti for reporting and
confirming this issue.
Some vector instructions override AsmString in the tablegen description,
but did not include the Apple syntax variant, so were printed without
operands.
Fixes#151330
These encodings were previously assigned to c.slli64/srli64/srai64, and
designated as hints for RV32 and RV64. Those mnemonics no longer appear
in the ISA manual after RV128 was removed. The spec now says that
c.slli/c.srli/c.srai with an immediate of 0 is a hint.
This patch updates the assembler to accept this. I've left the old
spelling for backwards compatibility but we disassemble a shift with a
zero immediate. The C_SLLI64_HINT/C_SRLI_HINT/C_SRAI_HINT instructions
are removed and the predicates for C_SLLI/C_SRLI/C_SRAI not accept a 0
immediate.
Fixes#150304
