The initial .reloc support for MIPS incorrectly interpreted .reloc 0 as .reloc .+0 .
I was misled when porting .reloc to other targets in 2019 and 2020.
Many PRINT: prefixes are unnecessary. The MCAsmStreamer implementation
is generic, and it is unnecessary to test too many variants.
Some SPARC ISA levels and/or extensions are defined in a way such that
the availability of it implies the availability of other, more fundamental
ISA features (for example, targeting 64-bit environment implies that
V9 instructions are available).
Properly set those in the TableGen definitions.
Fixes https://github.com/llvm/llvm-project/issues/142388.
* adjustFixupValue is called even when a R_SPARC_HIX22/R_SPARC_LOX10
relocation is generated. This will be fixed shortly.
* Enhanced the %h44 test to show that we don't check overflow.
* Test R_SPARC_DISP32 in .gcc_except_table and .eh_frame . The original
support did not test -filetype=obj output.
1bfc5e7 introduced support for `%gdop_hix22()` and `%gdop_lox10()`.
However, it incorrectly mapped them to `R_SPARC_GOTDATA_HIX22` and
`R_SPARC_GOTDATA_LOX10`. They should in fact emit
`R_SPARC_GOTDATA_OP_HIX22` and `R_SPARC_GOTDATA_OP_LOX10`.
This became a problem when assembling glibc's PIC startup code:
```asm
sethi %gdop_hix22(main), %o0
xor %o0, %gdop_lox10(main), %o0
ldx [%l7 + %o0], %o0, %gdop(main)
```
After the `xor`, `%o0` should contain the GOT offset for `main`, but
because of the incorrect relocations, it actually ends up containing the
address of `main`, which of course makes the following `ldx` fail.
https://reviews.llvm.org/D47136 did not correctly handle `ld [%i0 + abs], %o0; abs = 7`
To fix it and make fixup handling less hacky,
* Change TableGen MEMri to use simm13Op instead of i32imm
* Emit a fixup of kind fixup_sparc_13 in SparcMCCodeEmitter::getSImm13OpValue
* Convert fixup_sparc_13 to either R_SPARC_13/R_SPARC_GOT13 in getRelocType
This postpones 13/GOT13 decision to relocation generation, ensuring that
we suppress the relocation when referencing an absolute symbol, matching
gas.
* Remove unuseful -filetype=asm -show-encoding output from relocation tests.
* Test STT_TLS for TLS relocations
* Test r_offset for a few relocations
* Test ASM output for many relocations
`call local` should perform STT_SECTION adjustment as well as `call .Ltmp0`.
The early support 9fc29098dfa684de53dd180aa93e94c39c388631 from 2014 was
confused.
The fixup output is a debug aid and should not be used to test
target-specific relocation generation implementation. The llvm-mc
-filetype=obj output is what truly matters.
Also fix up any mistakes/typos in instruction definitions.
Reviewers: rorth, s-barannikov, brad0, MaskRay
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/130967
Implement handling for `v8plus` feature bit to allow the user to switch
between V8 and V8+ mode with 32-bit code.
Currently this only sets the appropriate ELF machine type and flags;
codegen changes will be done in future patches.
This is done as a prerequisite for `-mv8plus` flag on clang (#98713).
Validate and reject any unknown or unavailable instruction mnemonics early
in ParseInstruction, before any operand parsing is performed. Some operands
(mainly memory ones) can be parsed slightly differently in V8 and V9
assembly language, so by rejecting unknown or unavailable instructions early
we can prevent the error message from being shadowed by the one raised during
operand parsing.
As a side effect this also allows us to tell unknown and unavailable
mnemonics apart, and issue a suggestion in appropriate cases.
This is based on the approach taken by the MIPS backend.
Reviewers: brad0, rorth, s-barannikov, jrtc27
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/96021
Emit the correct machine type when writing out ELF objects.
This patch is modeled on GCC's behavior:
- `-m32` emits an object of type EM_SPARC;
- `-m32 -mcpu=v9` emits EM_SPARC32PLUS (however, see below); and
- `-m64` emits EM_SPARCV9.
Note that GCC does not guarantee emission of EM_SPARC32PLUS objects,
since GNU as doesn't support user control of emitted machine type.
It will always autodetect the type based on the instruction mix:
- If there's a V9 instruction inside, then emit EM_SPARC32PLUS; and
- Emit EM_SPARC otherwise.
For LLVM we choose deterministic behavior instead for simplicity.
Unify parts of ASI and Prefetch tag matching at `parseASITag`
and `parsePrefetchTag` to use a common function to parse any immediate
expressions. This introduces a slight regression to error messages,
but is needed so we can enable `ParseForAllFeatures`
in `MatchOperandParserImpl` in a future patch.
Reviewers: jrtc27, brad0, rorth, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/96020
This adds the alternate mnemonics for movrz and movrnz.
Reviewers: s-barannikov, jrtc27, brad0, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94252
This adds support for `prefetcha` instruction for prefetching from
alternate address spaces.
Reviewers: jrtc27, brad0, rorth, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94250
This adds named tag constants (such as `#one_write` and `#one_read`)
for the prefetch instruction.
Reviewers: jrtc27, rorth, brad0, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94249
This adds %set_softint and %clear_softint alias for %asr20 and %asr21
as defined in JPS1.
Reviewers: jrtc27, brad0, s-barannikov, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94247
This adds support for GNU %uhi and %ulo extensions.
Those resolve to the same relocations as %hh and %hm.
Reviewers:
cyndyishida, dcci, brad0, jrtc27, aaupov, Endilll, rorth, maksfb, #reviewers-libcxxabi, s-barannikov, rafaelauler, ayermolo, #reviewers-libunwind, #reviewers-libcxx, daniel-grumberg, tbaederr
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94246
Transform `addc imm, %rs, %rd` into `addc %rs, imm, %rd`.
This is used in some GNU and Linux code.
Reviewers: s-barannikov, rorth, jrtc27, brad0
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94245
The issue is uncovered by #47698: for assembly files, -triple= specifies the
full target triple while -arch= merely sets the architecture part of the default
target triple, leaving a target triple which may not make sense, e.g.
riscv64-apple-darwin.
Therefore, -arch= is error-prone and not recommended for tests. The issue has
been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it
outrightly.
Due to the nature of the issue, we don't see the issue in tests using
architectures that any of Mach-O/COFF/XCOFF supports.
This adds some commonly-used instruction aliases from various sources:
- GNU
- SPARCv9 manual
- JPS1 ASR names
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157236
This adds named ASI tag constants (such as #ASI_P and #ASI_P_L) for memory
accesses.
This patch adds 64-bit/V9 tag names, given that currently the majority of SPARC
software targets that arch.
Support for 32-bit/V8 tag names will be added in a future patch.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157235
This completes the support for the CAS instructions.
Besides the base CASA and CASXA forms, on v9 the aliases CAS, CASX, CASL, and
CASXL are also available.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157234
This extends support for ASI-tagged loads, stores, and swaps with the new
stored-ASI form ([reg+imm] %asi) introduced in v9.
CAS instructions are handled differently by the (dis-)assembler, so it will be
handled in a separate patch.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157233
While both SPARCv7/v8 and v9 has a register named %fq, they encode it
differently, so we need to differentiate between them.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157232
This adds definitions for SPARC v9 State Registers (privileged/nonprivileged,
see v9 manual ch. 5).
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157231
This adds the v9 SETX pseudoinstruction for convenient loading of 64-bit values.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157230
Add support for DONE, RETRY, SAVED, and RESTORED (v9 Section A.11 & Section A.47).
Those instructions are used for low-level interrupt handling and register window
management by OS kernels.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D144936
Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third state: the
directive is not target specific. AsmParser::parseStatement detected
this case by using a fragile heuristic: if the target parser did not
consume any tokens, the directive is assumed to be not target-specific.
Some targets fail to follow the convention: they return success after
emitting an error or do not consume the entire line and return failure
on successful parsing. This was partially worked around by checking for
pending errors in parseStatement.
This patch tries to improve the situation by introducing parseDirective
method that returns ParseStatus -- three-state class. The new method
should eventually replace the old one returning bool.
ParseStatus is intentionally implicitly constructible from bool to allow
uses like `return Error(Loc, "message")`. It also has a potential to
replace OperandMatchResulTy as it is more convenient to use due to the
implicit construction from bool and more type safe.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D154101
This is a follow-up to b71edfaa4ec3c998aadb35255ce2f60bba2940b0
since I forgot the lit.local.cfg files in that one.
Reformatting is done with `black`.
If you end up having problems merging this commit because you
have made changes to a python file, the best way to handle that
is to run git checkout --ours <yourfile> and then reformat it
with black.
If you run into any problems, post to discourse about it and
we will try to help.
RFC Thread below:
https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style
Reviewed By: barannikov88, kwk
Differential Revision: https://reviews.llvm.org/D150762
Make sure that the upper bits of the offset is placed in bits 20-21 of the
instruction word.
This fixes the encoding of backwards (negative offset) BPr branches.
(Previously, the upper two bits of the offset would overwrite parts of the rs1
field, causing it to branch on the wrong register, with the wrong offset)
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D144012
