9 Commits

Author SHA1 Message Date
Andres-Salamanca
7e9927127f
[CIR] Fix outdated bitfield iteration logic in accumulateFields (#151741)
This PR fixes the outdated logic for accumulating bitfields in
`accumulateFields`. The old approach remained after the algorithm was
updated. A non-bitfield member would act as a barrier, causing
`accumulateBitFields` to receive an incomplete range of fields. As a
result, it failed to accumulate them properly when clipping was
necessary.

For reference, in ClangIR we already handle this correctly:

[b647f4b97b/clang/lib/CIR/CodeGen/CIRRecordLayoutBuilder.cpp (L711-L714))
2025-08-02 09:39:51 -05:00
Andres-Salamanca
97eec759e6
[CIR] Add support for binary operations on bitfield members (#149676)
This PR introduces support for binary operations on bitfield members.
2025-07-23 10:03:41 -05:00
Andres-Salamanca
b02787d33f
[CIR] Fix alignment when lowering set/get bitfield operations (#148999)
This PR fixes incorrect alignment when lowering `set` and `getBitField`
operations to LLVM IR. The issue occurred because during lowering, the
function was being called with an alignment of 0, which caused it to
default to the alignment of the packed member. For example, if the
bitfield was packed inside a `u64i`, it would use an alignment of 8.
With this change, the generated code now matches what the classic
codegen produces.
In the assembly format, I changed to be similar to how it's done in
loadOp. If there's a better approach, please feel free to point it out.
2025-07-18 16:13:34 -05:00
Andres-Salamanca
fdbd9c19c9
[CIR] Add support for unary operations on bitfield members (#148083)
This PR introduces support for unary operations on bitfield members.
Support for binary operations is planned for a future PR.
2025-07-14 12:57:38 -05:00
Andres-Salamanca
78e0c76789
[CIR][NFC] Add example for get_bitfield with volatile qualifier (#147828)
The example demonstrates how `get_bitfield` is emitted when accessing a
bitfield declared as `volatile`.
2025-07-10 18:05:58 -05:00
Andres-Salamanca
3d08a40959
[CIR] Upstream new SetBitfieldOp for handling C and C++ struct bitfields (#147609)
This PR upstreams the `set_bitfield` operation used to assign values to
bitfield members in C and C++ struct types.
Handling of AAPCS-specific volatile bitfield semantics will be addressed
in a future PR.
2025-07-10 15:16:29 -05:00
Andres-Salamanca
7563531fc9
[CIR] Add test for parsing bitfield_info attribute (#147628)
This PR adds a test for parsing the bitfield_info attribute.
Additionally, it updates the `storage_type` and `is_signed` fields to
match the style used in the incubator ASM format guide.
2025-07-09 16:03:47 -05:00
Andres-Salamanca
717899ce86
[CIR] Upstream get_bitfield operation to load bit-field members from structs (#145971)
This PR adds support for loading bit-field members from structs using
the `get_bitfield` operation.
It enables retrieving the address of the bitfield-packed member but does
**not** yet support volatile bitfields this will be addressed in a
future PR.
2025-07-02 18:05:19 -05:00
Andres-Salamanca
bd36f7331a
[CIR] Add initial support for bitfields in structs (#142041)
This change adds support for bitfields CIR records can now contain bit
fields.

I’ve updated the `CIRGenBitFieldInfo` comment, which originally came
from the incubator and was identical to the one in OGCodeGen, to better
reflect the current implementation.

Support for bitfields in unions big-endian architectures and `get` and
`set` operations remains unimplemented and will be addressed in a future
patch.
2025-06-20 09:03:02 -05:00