An example of this is the -mpure-code option. Without a config file
being used, an error message will print `-mpure-code`. But if a config
file is used, the error message will print `-mexecute-only`.
When generating armv6-m (Thumb1) Position Independent (PI) code
there are currently some code sequences that are not compatible
with eXecute-Only (XO) code.
For example, this simple code sequence when compiler for XO & PI:
extern int x;
int fn() { return x; }
is a problem as the address of x is currently loaded by:
ldr r0, .L0
:
:
.L0:
.long x
which is not XO compiant as this involves reading the value at
.L0 which is in the code section. Generating correct code is
currently hindered by lack of suitable relocations.
Disallow the generation of armv6-m PI code together with XO code
until they can be made to work together.
Differential Revision: https://reviews.llvm.org/D157620
Since D149444 this test has been failing with -Wmissing-multilib if
multilib is configured for the BareMetal toolchain.
By setting sysroot the test is more hermetic and the failure is avoided.
This patch moves the overall lower-bound arch restriction for Arm XO sections
from v8m to v6m. Actual implementation of code-gen for v6m will follow in
follow-up patches, which will include an implementation of relocations needed to
support this.
Reviewed By: simonwallis2, MaskRay
Differential Revision: https://reviews.llvm.org/D149444
With this, `clang-cl /source-charset:utf-16 test.cc` now prints `invalid
value 'utf-16' in '/source-charset:utf-16'` instead of `invalid value
'utf-16' in '-finput-charset=utf-16'` before, and several other clang-cl
flags produce much less confusing output as well.
Fixes PR29106.
Since an arg and its alias can have different arg types (joined vs not)
and different values (because of AliasArgs<>), I chose to give the Alias
its own Arg object. For convenience, I just store the alias directly in
the unaliased arg – there aren't many arg objects at runtime, so that
seems ok.
Finally, I changed Arg::getAsString() to use the alias's representation
if it's present – that function was already documented as being the
suitable function for diagnostics, and most callers already used it for
diagnostics.
Implementation-wise, Arg::accept() previously used to parse things as
the unaliased option. The core of that switch is now extracted into a
new function acceptInternal() which parses as the _aliased_ option, and
the previously-intermingled unaliasing is now done as an explicit step
afterwards.
(This also changes one place in lld that didn't use getAsString() for
diagnostics, so that that one place now also prints the flag as the user
wrote it, not as it looks after it went through unaliasing.)
Differential Revision: https://reviews.llvm.org/D64253
llvm-svn: 365413
The option -mexecute-only is translated into the backend option
-arm-execute-only. But this option only makes sense for the compiler and
the assembler does not recognize it. This patch stops clang from passing
this option to the assembler.
Change-Id: I4f4cb1162c13cfd50a0a36702a4ecab1bc0324ba
Review: https://reviews.llvm.org/D30414
llvm-svn: 296454
Summary:
This implements execute-only support for ARM code generation, which
prevents the compiler from generating data accesses to code sections.
The following changes are involved:
* Add the CodeGen option "-arm-execute-only" to the ARM code generator.
* Add the clang flag "-mexecute-only" as well as the GCC-compatible
alias "-mpure-code" to enable this option.
* When enabled, literal pools are replaced with MOVW/MOVT instructions,
with VMOV used in addition for floating-point literals. As the MOVT
instruction is required, execute-only support is only available in
Thumb mode for targets supporting ARMv8-M baseline or Thumb2.
* Jump tables are placed in data sections when in execute-only mode.
* The execute-only text section is assigned section ID 0, and is
marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'.
This also overrides selection of ELF sections for globals.
Reviewers: t.p.northover, rengolin
Subscribers: llvm-commits, aemerson
Differential Revision: https://reviews.llvm.org/D27450
llvm-svn: 289786
