The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`
However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`
The latter form is also more flexible as it allows reordering output
operands.
In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.
Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.
1. BinOp*, UnaryOp* will be used in X86InstrShiftRotate.td for the APX
support
2. Simplify CRC32 definitions to extract the NFC change in 76434 into a
separate commit
1. Remove these two classes b/c opcode is changed from 0xF6 to 0x66
after promotion, then the classes become useless.
2. Remove `OpSize = OpSizeFixed` b/c the default value is OpSizeFixed.
3. Remove `let isCommutable = 1` b/c ADCX/ADOX is not VEX-encoding,
we can not apply VEX3ToVEX2 optimization for it and the compiler
never emits it.
4. Remove predicate `HasADX` due to no pattern
This patch is to extract the NFC in #76319 into a separate commit.
For legacy (arithmetic) instructions, the operand size override prefix (0x66)
is used to switch the operand data size from 32b to 16b (in 32/64-bit mode),
16b to 32b (in 16-bit mode). That's why we set OpSize16 for 16-bit instructions
and set OpSize32 for 32-bit instructions.
But it's not a generic rule any more after APX. APX adds 4 variants for
arithmetic instructions: promoted EVEX, NDD (new data destination), NF (no flag),
NF_NDD. All the 4 variants are in EVEX space and only legal in 64-bit
mode. EVEX.pp is set to 01 for the 16-bit instructions to encode 0x66.
For APX, we should set OpSizeFixed for 8/16/32/64-bit variants and set PD for
the 16-bit variants.
Hence, to reuse the classes ITy and its subclasses BinOp* for APX instructions,
we extract the OpSize setting from the class ITy.
It helps simplify the class definitions. Now, the only explicit usage of PS is
to check prefix 0x66/0xf2/0xf3 can not be used a prefix, e.g. wbinvd.
See 82974e0114f02ffc07557e217d87f8dc4e100a26 for more details.
This can help us aovid introducing new classes T_MAP*PS|PD|XS|XD
when a new opcode map is supported.
And, T_MAP*PS|PD|XS|XD does not look better than T_MAP*, PS|PD|XS|XD.
`VEX_4V` does not look simpler than `VEX, VVVV`. It's kind of confusing
b/c classes like `VEX_L`, `VEX_LIG` do not imply `VEX` but it does.
For APX, we have promote EVEX, NDD, NF and NDD_NF instructions. All of
the 4 variants are in EVEX space and NDD/NDD_NF set the VVVV fields.
To extract the common fields (e.g EVEX) into a class and set VVVV
conditionally, we need VVVV to not imply other prefixes.
According to Intel SDE, ADCX reads CF and ADOX reads OF. `Uses` was
set to empty by accident, the bug was not exposed b/c compiler never
emits these instructions.
1. Simplify the variable name
2. Change HasOddOpcode to HasEvenOpcode b/c
a. opcode of any 8-bit arithmetic instruction is even
b. opcode of a 16/32/64-bit arithmetic instruction is usually
odd, but it can be even sometimes, e.g. INC/DEC, ADCX/ADOX
c. so that we can remove `let Opcode = o` for the mentioned corner
cases.
1. Remove redandunt classes
2. Correct comments
3. Move duplicated `let` statement into class definition
4. Simplify the variable name and align the code
1. Move all pattern fragments for SIMD instructions to X86InstrFragmentsSIMD.td
2. Create X86InstrFragments.td and move non-SIMD pattern fragments into it
3. Create X86InstrOperands.td and move operand definitions into it
4. Create X86InstrPredicates.td and move predicate definitions into it
5. Create X86InstrUtils.td and move utilities for simplifying the instruction definitions into it
D150436 changed the order for INC*r, but unintentionally remove 'isConvertibleToThreeAddress = 1' for INC*r_alt.
This patch also update wrong comment X86InstrArithmetic.td, and move class ITy to InstrInfo.td for it's a general class.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D151527
This caused compiler assertions, see comment on
https://reviews.llvm.org/D150107.
This also reverts the dependent follow-up change:
> [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
>
> This is follow-up of D150107.
>
> In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
> shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.
>
> Differential Revision: https://reviews.llvm.org/D150949
This reverts commit 2ef8ae134828876ab3ebda4a81bb2df7b095d030 and
5586bc539acb26cb94e461438de01a5080513401.
This is follow-up of D150107.
In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.
Differential Revision: https://reviews.llvm.org/D150949
The logic from line 633 to 640 is specific for ARM as the comments said, it will make all the targets will prefer to using instruction with more predicates when compiler do AsmMatching.
And for code from line 642 to 649, X86 want to use the order records written in source file to sort the instructions. So X86 could be affected by this logic. (These code could be arrived only by X86)
After change this, seems AVX instructions have not be affected but it exposed some other errors for instruction push and call.
CALLpcrel16 could not be used in 64 bit mode, we need add Predicate for it. And for push instruction, previously because pushi32 has predicates = [Not64bitmode], so it precede pushi16, which is incorrect here, we should get pushw here and it also align with gcc.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D150436
In this file, most of the line don't have trailing spaces,
but some of them have. To keep consistent, remove the trailing
spaces.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D146697
Fix some bugs and reland e4c1dfed38370b4 and 614c63bec6d67c.
1. Run argument stack rebase pass before the reserved physical register
is finalized.
2. Add LEA pseudo instruction to prevent the instruction being
eliminated.
3. Don't support X32.
1. Extract the common code of some instructions into a class to reduce duplication
2. Refine some comments to the make the description of the class clearer
By this way, the records defined here will be consistent and easier to
maintain, I think.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D144154
For now X86InstrInfo.td has many definitions for some instrs
and patterns which I think should not exist here, extract them
and move to other files.
It will be more clear to me that X86InstrInfo just define some
X86 specific properties and would not include detailed instrs
definition.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D144244
