479 Commits

Author SHA1 Message Date
Matt Arsenault
a6fc489bb7
AMDGPU: Add gfx950 subtarget definitions (#116307)
Mostly a stub, but adds some baseline tests and
tests for removed instructions.
2024-11-18 10:41:14 -08:00
Freddy Ye
97836bed63
Reland "[X86] Support -march=diamondrapids (#113881)" (#116564)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-18 10:40:32 +08:00
Freddy Ye
90e92239bd
Revert "[X86] Support -march=diamondrapids (#113881)" (#116563)
This reverts commit 826b845c9e97448395431be3e4e5da585bd98c5e.
2024-11-18 08:45:28 +08:00
Freddy Ye
826b845c9e
[X86] Support -march=diamondrapids (#113881)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-18 08:31:17 +08:00
SpencerAbson
748b028540
[AArch64] Make +sve2-aes an alias of +sve2+sve-aes (#116026)
This patch essentially re-lands
https://github.com/llvm/llvm-project/pull/114293 with the following
fixups

- `nosve2-aes` should disable the backend feature `FeatureSVEAES` such
that the set of existing instructions that this removes is unchanged.
- FMV dependencies now use the autogenerated `ExtensionDepencies`
structure (since https://github.com/llvm/llvm-project/pull/113281) so we
do not require the change to `AArch64FMV.td`.
2024-11-14 11:04:04 +00:00
tangaac
2283d50447
[LoongArch] add la v1.1 features for sys::getHostCPUFeatures (#115832)
Two features (i.e. `frecipe` and `lam-bh`) are added to
`sys.getHostCPUFeatures`. More features will be added in future.

In addition, this patch adds the features returned by
`sys.getHostCPUFeature` when `-march=native`.
2024-11-14 11:25:32 +08:00
Elvina Yakubova
133f8fa233
Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (#115467)
…eatures in cpu info

Relands #97749. Fixed test by adding additional checks for system linux
and target == host.
2024-11-13 09:10:56 +00:00
Shilei Tian
de0fd64bed
[AMDGPU] Introduce a new generic target gfx9-4-generic (#115190)
This patch introduces a new generic target, `gfx9-4-generic`. Since it doesn’t support FP8 and XF32-related instructions, the patch includes several code reorganizations to accommodate these changes.
2024-11-12 23:11:05 -05:00
Jim Lin
956361ca08
[RISCV] Zabha/Zacas implies Zaamo (#115694)
The Zabha/Zacas extension depends upon the Zaamo extension. 
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.
2024-11-12 15:49:34 +08:00
Malay Sanghi
f77101ea79
[X86][AMX] Support AMX-MOVRS (#115151)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-12 15:05:43 +08:00
Feng Zou
eddb79d56d
[X86][AMX] Support AMX-TF32 (#115625)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-11 15:24:18 +08:00
Phoebe Wang
8f4401374c
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
2024-11-09 13:26:10 +08:00
Alan Zhao
ff22515430
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070

Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
2024-11-08 16:15:02 -08:00
Phoebe Wang
58a17e1bbc
[X86][AMX] Support AMX-AVX512 (#114070) 2024-11-08 16:25:16 +08:00
Phoebe Wang
c72a751dab
[X86][AMX] Support AMX-TRANSPOSE (#113532)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-01 16:45:03 +08:00
Feng Zou
8127162427
[X86][AMX] Support AMX-FP8 (#113850)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-31 10:14:25 +08:00
Craig Topper
94e7d9c0bf [RISCV] Remove Zvk* dependency checks from RISCVISAInfo::checkDependency.
The Zvk* extensions now imply Zve32x or Zve64x so it shouldn't be
possible to fail these dependency checks.
2024-10-29 13:57:23 -07:00
Elvina Yakubova
80a09735ac
Revert "[clang][AArch64] Add getHostCPUFeatures to query for enabled … (#114066)
…features in cpu info (#97749)"

This reverts commit d732c0b13c55259177f2936516b6087d634078e0.

This is breaking buildbots
https://lab.llvm.org/buildbot/#/builders/190/builds/8413,
https://lab.llvm.org/buildbot/#/builders/56/builds/10880 and a few
others.
2024-10-29 14:43:01 +00:00
neildhickey
d732c0b13c
[clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (#97749)
Add getHostCPUFeatures into the AArch64 Target Parser to query the 
cpuinfo for the device in the case where we are compiling with 
-mcpu=native.
Add LLVM_CPUINFO environment variable to test mock /proc/cpuinfo
files for -mcpu=native

Co-authored-by: Elvina Yakubova <eyakubova@nvidia.com>
2024-10-29 13:34:43 +00:00
Freddy Ye
c4248fa3ed
[X86] Support MOVRS and AVX10.2 instructions. (#113274)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-25 09:00:19 +08:00
tangaac
5b9c76b6e7
[LoongArch] Support LoongArch-specific amswap[_db].{b/h} and amadd[_db].{b/h} instructions (#113255)
Two options for clang: -mlam-bh & -mno-lam-bh.
Enable or disable amswap[__db].{b/h} and amadd[__db].{b/h} instructions.
The default is -mno-lam-bh.
Only works on LoongArch64.
2024-10-23 16:03:15 +08:00
Carl Ritson
076aac59ac
[AMDGPU] Add a new target for gfx1153 (#113138) 2024-10-23 12:56:58 +09:00
Freddy Ye
9e3d4653af
[X86] Update Model value for Arrow Lake. (#113273)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-23 09:44:26 +08:00
hpoussin
c6ba7b38db
[Triple] Make mipsel-*-windows-* use COFF files by default (#107809)
Windows NT/MIPS and Windows CE/MIPS always used COFF format.

This is an extract of PR #107744.
2024-10-15 10:49:17 +08:00
Albert Huang
aa2c0f35a1
[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU (#110085)
STAR-MC1 is an Armv8m CPU.

Technical specifications available at:

https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160
2024-10-14 15:48:12 +01:00
Michał Górny
387b37af1a
[LLVM] [Clang] Support for Gentoo *t64 triples (64-bit time_t ABIs) (#111302)
Gentoo is planning to introduce a `*t64` suffix for triples that will be
used by 32-bit platforms that use 64-bit `time_t`. Add support for
parsing and accepting these triples, and while at it make clang
automatically enable the necessary glibc feature macros when this suffix
is used.

An open question is whether we can backport this to LLVM 19.x. After
all, adding new triplets to Triple sounds like an ABI change — though I
suppose we can minimize the risk of breaking something if we move new
enum values to the very end.
2024-10-14 11:18:04 +00:00
RipleyTom
c5f7a32356
[X86] Add AMD Llano family detection (#111312)
Very simple one liner, adds the missing detection for the Llano family
which is essentially a refreshed K10:
Documentation of the family id:
https://en.wikichip.org/wiki/amd/cpuid#Family_18_.2812h.29
Documentation that it fits into amdfam10:
https://en.wikipedia.org/wiki/AMD_10h#12h
2024-10-07 08:33:26 -07:00
Yingwei Zheng
bf895c714e
[RISCV] Bump hwprobe support to Linux 6.11 (#108578)
This patch is the follow-up of
https://github.com/llvm/llvm-project/pull/94352 with some updates:
1. Add support for more extensions for `zve*`, `zimop`, `zc*`, `zcmop`
and `zawrs`.
2. Use `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF` to check whether the
processor supports fast misaligned scalar memory access.
https://github.com/llvm/llvm-project/pull/108551 reminds me that the
patch
https://lore.kernel.org/all/20240809214444.3257596-1-evan@rivosinc.com/T/
has been merged. Address comment
https://github.com/llvm/llvm-project/pull/94352#discussion_r1626056015.

References:
1. constants:
https://github.com/torvalds/linux/blame/v6.11-rc7/arch/riscv/include/uapi/asm/hwprobe.h
2. https://docs.kernel.org/arch/riscv/hwprobe.html
3. Related commits:
1. `zve*` support:
de8f8282a9
2. `zimop` support:
36f8960de8
3. `zc*` support:
0ad70db5eb
4. `zcmop` support:
fc078ea317
5. `zawrs` support:
244c18fbf6
6. scalar misaligned perf:
c42e2f0767
and
1f5288874d
2024-10-05 11:00:09 +08:00
Jonathan Thackray
d0756caedc
[ARM][AArch64] Introduce the Armv9.6-A architecture version (#110825)
This introduces the Armv9.6-A architecture version, including the
relevant command-line option for -march.

More details about the Armv9.6-A architecture version can be found at:
  * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2024
  * https://developer.arm.com/documentation/ddi0602/2024-09/
2024-10-04 10:12:41 +01:00
Piyou Chen
a2994ded60
[RISCV] Fix RISCVBitPositions typo (#110953)
This patch updates  `{"zve64x", 0, 63},` into `{"zve64f", 0, 63},`.

Base on
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions
2024-10-03 14:34:44 +08:00
Jubilee
b8028f6b87
[TargetParser][AArch64] Believe runtime feature detection (#95694)
In https://github.com/llvm/llvm-project/issues/90365 it was reported
that TargetParser arrives at the wrong conclusion regarding what
features are enabled when attempting to detect "native" features on the
Raspberry Pi 4, because it (correctly) detects it as a Cortex-A72, but
LLVM (incorrectly) believes all Cortex-A72s have crypto enabled. Attempt
to help ourselves by allowing runtime information derived from the host
to contradict whatever we believe is "true" about the architecture.
2024-10-02 08:28:57 +01:00
Alex Bradbury
614aeda93b
[RISCV] Mark Zacas as non-experimental (#109651)
The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. The
ABI issue has been resolved by #101023 so I believe there's no known
barrier to moving Zacas to non-experimental.
2024-09-25 06:14:43 +01:00
Alex Rønne Petersen
72a218056d
[llvm][Triple] Add Environment members and parsing for glibc/musl parity. (#107664)
This adds support for:

* `muslabin32` (MIPS N32)
* `muslabi64` (MIPS N64)
* `muslf32` (LoongArch ILP32F/LP64F)
* `muslsf` (LoongArch ILP32S/LP64S)

As we start adding glibc/musl cross-compilation support for these
targets in Zig, it would make our life easier if LLVM recognized these
triples. I'm hoping this'll be uncontroversial since the same has
already been done for `musleabi`, `musleabihf`, and `muslx32`.

I intentionally left out a musl equivalent of `gnuf64` (LoongArch
ILP32D/LP64D); my understanding is that Loongson ultimately settled on
simply `gnu` for this much more common case, so there doesn't *seem* to
be a particularly compelling reason to add a `muslf64` that's basically
deprecated on arrival.

Note: I don't have commit access.
2024-09-20 08:53:03 +08:00
Ganesh
02e4186d0b
[X86] AMD Zen 5 Initial enablement (#107964)
This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
2024-09-13 17:45:33 +01:00
Kazu Hirata
33e7cd6ff2
[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)
S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
than slice thanks to std::string_view::substr.
2024-08-25 11:30:49 -07:00
Craig Topper
371f936c45 [RISCV] Make extension names lower case in RISCVISAInfo::checkDependency() error messages. 2024-08-19 00:22:28 -07:00
Craig Topper
10a4f1ef9e [RISCV] Add helper functions to exploit similarity of some RISCVISAInfo::checkDependency() error strings. NFC 2024-08-19 00:22:28 -07:00
Craig Topper
d489b7ccb7 [RISCV] Merge some ISA error reporting together and make some errors more precise.
Loop over the extension names that have the same error message.

Print the name of Zvk* extensions instead of 'zvk*'.
2024-08-19 00:22:28 -07:00
Pengcheng Wang
a80a90e34b
[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)
These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
2024-08-19 11:50:32 +08:00
Piyou Chen
82f52d9c42
[RISCV] Support new groupid/bitmask for cpu_model (#101632)
The spec can be found at
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

1. Add the new extension GroupID/Bitmask with latest hwprobe key.
2. Update the `initRISCVFeature `
3. Update `EmitRISCVCpuSupports` due to not only group0 now.
2024-08-08 14:42:41 +08:00
Aaron Ballman
617cf8a72d
Reapply "Finish deleting the le32/le64 targets" (#99079) (#101983)
This reverts commit d3f8105c65046173e20c4c59394b4a7f1bbe7627.

Halide no longer relies on this target:
https://github.com/llvm/llvm-project/pull/98497#issuecomment-2253358685
2024-08-06 08:35:56 -04:00
Phoebe Wang
259ca9ee9c
Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (#101616)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-03 09:26:07 +08:00
Phoebe Wang
2e0588d5e1
Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions" (#101612)
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.
2024-08-02 13:04:10 +08:00
Phoebe Wang
10bad2c8d7
[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-02 12:10:50 +08:00
Shengchen Kan
95e9afff30 [X86] Update sub-features of APX for host CPU
This is a follow-up for https://github.com/llvm/llvm-project/pull/80636
2024-07-30 18:09:58 +08:00
Chen Zheng
d311edd0ef [PowerPC] fix default cpu setting
for platform that returns nothing for getHostCPUName()
For example for target ARM on windows. For this case, -mcpu=native
should set CPU to the default according to triple instead of setting
CPU to "native"

Fixes https://lab.llvm.org/buildbot/#/builders/161/builds/873 caused by
https://github.com/llvm/llvm-project/pull/97541
2024-07-25 09:55:00 -04:00
Kazu Hirata
74fcb6aafd [TargetParser] Fix warnings
This patch fixes:

  llvm/include/llvm/TargetParser/PPCTargetParser.def:109:9: error:
  suggest braces around initialization of subobject
  [-Werror,-Wmissing-braces]

  llvm/lib/TargetParser/PPCTargetParser.cpp:96:16: error: address of
  stack memory associated with local variable 'CPU' returned
  [-Werror,-Wreturn-stack-address]
2024-07-24 23:57:53 -07:00
Chen Zheng
25482b356e
[PowerPC] add TargetParser for PPC target (#97541)
For now only focus on the CPU type, will work on the CPU features part
later.

With the CPU handling in TargetParser, clang and llc/opt are able to
query common interfaces.

So we can set same default CPU and CPU features with same interfaces.
2024-07-25 13:46:59 +08:00
Aiden Grossman
599f8e1120 Reland "[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)"
This reverts commit f1905f064451bf688577976a13000c9c47e58452.

This relands commit 19cf8deabe1124831164987f1b9bf2f806c0a875.

There were issues with the preprocessor includes that should have
excluded MSVC still including clang functions building on windows and
using intrin.h. This relanding fixes this behavior by additionally
wrapping the uses of __get_cpuid and __get_cpuid_count in _MSC_VER so
that clang in MSVC mode, which includes intrin.h, does not have any
conflicts.
2024-07-24 03:58:23 +00:00
Philip Reames
d1e28e2a7b
[RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (#99700)
This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.

This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins (which
have a much narrower user interface), and the avoidance of false
generality. This change deliberately only handles group 0 extensions
(which happen to be all defined ones today), and avoids the tblgen
changes from that review.

I don't have an environment in which I can actually test this, but @BeMg
has been kind enough to report that this appears to work as expected.

Before this can make it into a release, we need a change such as
https://github.com/llvm/llvm-project/pull/99958. The gcc docs claim that
cpu_support can be called by "normal" code without calling the cpu_init
routine because the init routine will have been called by a high
priority constructor. Our current compiler-rt mechanism does not do
this.
2024-07-23 08:48:28 -07:00