2399 Commits

Author SHA1 Message Date
AZero13
6a425f1e54
[ARM] Have custom lowering for ucmp and scmp (#149315)
Limited to non-thumb1 for scmp at the moment, since there is no good way
to do it.
2025-08-08 06:51:18 +01:00
Kazu Hirata
62fc0028bf
[Target] Remove unnecessary casts (NFC) (#152262)
value() already returns uint64_t.
2025-08-06 07:11:07 -07:00
eleviant
907b7d0f07
[ARM] Fix inline asm register validation for vector types (#152175)
Patch allows following piece of code to be successfully compiled:
```
register uint8x8_t V asm("d3") = vdup_n_u8(0xff);
```
2025-08-06 10:30:49 +02:00
Matt Arsenault
342bf58f93
RuntimeLibcalls: Add entries for __security_check_cookie (#151843)
Avoids hardcoding string name based on target, and gets
the entry in the centralized list of emitted calls.
2025-08-06 10:26:36 +09:00
Matt Arsenault
d44754c344
ARM: Remove redundant or buggy config of __aeabi_d2h (#152126)
This was set if `TT.isTargetAEABI()`. This was previously set above
if `TM.isAAPCS_ABI() && (TT.isTargetAEABI() || TT.isTargetGNUAEABI() ||
                         TT.isTargetMuslAEABI() || TT.isAndroid())`.

So this could differ based on a manually specified -target-abi flag due
to the `isAAPCS_ABI` part of the original condition. I'm guessing
these should be consistent, so either this second group of
setLibcallImpl
calls should have been guarded by the `isAAPCS_ABI` check, or the first
condition should remove it.

There doesn't appear to be any meaningful test coverage using the
manually specified ABI option, so #152108 tries to remove it
2025-08-06 08:48:01 +09:00
Matt Arsenault
1392edcc07
ARM: Remove idiv runtime call aliases (#152098)
Really only the i32 variants exist. We don't need synthetic
aliases for illegal types which will be promoted.
2025-08-05 17:49:22 +09:00
AZero13
23022a4683
[SelectionDAG] Move sign pattern check from AArch64 and ARM to general SelectionDAG (#151736)
This works on all cases much like the XOR case above it in SelectionDAG.
2025-08-01 14:46:51 -07:00
Prabhu Rajasekaran
17ccb849f3
[llvm] Extract and propagate callee_type metadata
Update MachineFunction::CallSiteInfo to extract numeric CalleeTypeIds
from callee_type metadata attached to indirect call instructions.

Reviewers: nikic, ilovepi

Reviewed By: ilovepi

Pull Request: https://github.com/llvm/llvm-project/pull/87575
2025-07-30 14:56:39 -07:00
Nikita Popov
fe0dbe0f29
[CodeGen] More consistently expand float ops by default (#150597)
These float operations were expanded for scalar f32/f64/f128, but not
for f16 and more problematically, not for vectors. A small subset of
them was separately set to expand for vectors.

Change these to always expand by default, and adjust targets to mark
these as legal where necessary instead.

This is a much safer default, and avoids unnecessary legalization
failures because a target failed to manually mark them as expand.

Fixes https://github.com/llvm/llvm-project/issues/110753.
Fixes https://github.com/llvm/llvm-project/issues/121390.
2025-07-28 09:46:00 +02:00
eleviant
a4796b14fc
[ARM] Emit error message when incompatible reg is specified (#147559)
At the moment the following piece of code causes undefined behavior:
```
int a;
void b() {
   register float d2 asm("d2") = a;
   asm("" ::"r"(d2));
}
```
This happens because variable and register types are incompatible.
2025-07-24 19:19:25 +02:00
Philip Reames
dbd9eae95a
[IA] Support vp.store in lowerinterleavedStore (#149605)
Follow up to 28417e64, and the whole line of work started with 4b81dc7.

This change merges the handling for VPStore - currently in
lowerInterleavedVPStore - into the existing dedicated routine used in
the shuffle lowering path. This removes the last use of the dedicated
lowerInterleavedVPStore and thus we can remove it.

This contains two changes which are functional.

First, like in 28417e64, merging support for vp.store exposes the
strided store optimization for code using vp.store.

Second, it seems the strided store case had a significant missed
optimization. We were performing the strided store at the full unit
strided store type width (i.e. LMUL) rather than reducing it to match
the input width. This became obvious when I tried to use the mask
created by the helper routine as it caused a type incompatibility.

Normally, I'd try not to include an optimization in an API rework, but
structuring the code to both be correct for vp.store and not optimize
the existing case turned out be more involved than seemed worthwhile. I
could pull this part out as a pre-change, but its a bit awkward on it's
own as it turns out to be somewhat of a half step on the possible
optimization; the full optimization is complex with the old code
structure.

---------

Co-authored-by: Craig Topper <craig.topper@sifive.com>
2025-07-22 15:50:17 -07:00
Philip Reames
28417e6459
[IA] Support vp.load in lowerInterleavedLoad [nfc-ish] (#149174)
This continues in the direction started by commit 4b81dc7. We
essentially merges the handling for VPLoad - currently in
lowerInterleavedVPLoad - into the existing dedicated routine. This
removes the last use of the dedicate lowerInterleavedVPLoad and thus we
can remove it.

This isn't quite NFC as the main callback has support for the strided
load optimization whereas the VPLoad specific version didn't. So this
adds the ability to form a strided load for a vp.load deinterleave with
one shuffle used.
2025-07-17 17:29:28 -07:00
Kazu Hirata
2da59287aa
[Target] Remove unnecessary casts (NFC) (#149342)
getFunction().getParent() already returns Module *.
2025-07-17 15:24:25 -07:00
Brad Smith
0d2e11f3e8
Remove Native Client support (#133661)
Remove the Native Client support now that it has finally reached end of life.
2025-07-15 13:22:33 -04:00
Simon Pilgrim
82a276e610
[ARM][WebAssembly] Remove unused PatternMatch namespace. NFC. (#147984)
Avoid file-level "using namespace llvm::PatternMatch" to make it easier to potentially use SDPatternMatch in the future.
2025-07-11 10:24:43 +01:00
AZero13
0edc98cd6d
[ARM] Copy SMAX(lhs, 0) and SMIN(lhs, 0) patterns from AArch64 to ARM (#146565)
They work on ARM too.
2025-07-10 21:06:52 +01:00
Matt Arsenault
d801b54bcd
ARM: Fix calling convention for gnu half conversion functions (#147951)
I'm surprised at how bad the test coverage is here. There is some
overlap with existing tests, but they aren't comprehensive and do
not cover all the ABIs, or all the different types.

Fixes #147935
2025-07-10 22:47:44 +09:00
Boyao Wang
697beb3f17
[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context (#147664)
Add LLVM Context to getOptimalMemOpType and findOptimalMemOpLowering. So
that we can use EVT::getVectorVT to generate EVT type in
getOptimalMemOpType.

Related to [#146673](https://github.com/llvm/llvm-project/pull/146673).
2025-07-10 11:11:09 +08:00
Matt Arsenault
deade03910
ARM: Unconditionally set eabi libcall calling convs in RuntimeLibcalls (#146083)
This fully consolidates all the calling convention configuration into
RuntimeLibcallInfo. I'm assuming that __aeabi functions have a universal
calling convention, and on other ABIs just don't use them. This will
enable splitting of RuntimeLibcallInfo into the ABI and lowering component.
2025-07-09 17:16:48 +09:00
Matt Arsenault
dc69b00b0a
RuntimeLibcalls: Remove table of soft float compare cond codes (#146082)
Previously we had a table of entries for every Libcall for
the comparison to use against an integer 0 if it was a soft
float compare function. This was only relevant to a handful of
opcodes, so it was wasteful. Now that we can distinguish the
abstract libcall for the compare with the concrete implementation,
we can just directly hardcode the comparison against the libcall
impl without this configuration system.
2025-07-09 17:13:58 +09:00
Matt Arsenault
dd9646565e ARM: Move sjlj libcall configuration to RuntimeLibcalls
Manually submitting, closes #147227
2025-07-08 13:52:32 +09:00
Matt Arsenault
591b0d0fdf
RuntimeLibcalls: Associate calling convention with libcall impls (#144979)
Instead of associating the libcall with the RTLIB::Libcall, put it
into a table indexed by the RTLIB::LibcallImpl. The LibcallImpls
should contain all ABI details for a particular implementation, not
the abstract Libcall. In the future the wrappers in terms of the
RTLIB::Libcall should be removed.
2025-07-08 10:20:52 +09:00
Matt Arsenault
2bd31edd57 ARM: Remove subtarget field tracking SjLj
This is a module level property that needs to be globally
consistent, so it does not belong in the subtarget.

Now that the Triple knows the default exception handling type,
consolidate the interpretation of None as select target default
exception handling in TargetMachine and use that. This enables
moving the configuration of UNWIND_RESUME to RuntimeLibcalls.

Manually submitting, closes #147226
2025-07-08 09:56:34 +09:00
Jay Foad
17d6aa01ec
[ARM] Fix expansion of ABS in a call sequence (#147270)
Fixes #147162
2025-07-07 15:52:37 +01:00
Matt Arsenault
d8ef156379
DAG: Remove verifyReturnAddressArgumentIsConstant (#147240)
The intrinsic argument is already marked with immarg so non-constant
values are rejected by the IR verifier.
2025-07-07 16:28:47 +09:00
AZero13
7d65cb1952
[ARM] Copy (SELECT_CC setgt, iN lhs, -1, 1, -1) -> (OR (ASR lhs, N-1), 1 from AArch64 to ARM (#146561)
It works perfectly for ARM too.
2025-07-05 18:17:33 +01:00
David Green
9fcea2e465 [ARM] Add neon vector support for roundeven
As per #142559, this marks froundeven as legal for Neon and upgrades the
existing arm.neon.vrintn intrinsics.
2025-07-04 15:27:33 +01:00
David Green
ec35065789 [ARM] Add neon vector support for rint
As per #142559, this marks frint as legal for Neon and upgrades the existing
arm.neon.vrintx intrinsics.
2025-07-03 21:27:48 +01:00
David Green
1f8f477bd0 [ARM] Add neon vector support for trunc
As per #142559, this marks ftrunc as legal for Neon and upgrades the existing
arm.neon.vrintz intrinsics.
2025-07-03 07:41:13 +01:00
David Green
5332534b9c [ARM] Add neon vector support for ceil
As per #142559, this marks fceil as legal for Neon and upgrades the existing
arm.neon.vrintp intrinsics.
2025-07-01 15:41:10 +01:00
David Green
6bd9ff04af [ARM] Add neon vector support for round
As per #142559, this marks fround as legal for Neon and upgrades the existing
arm.neon.vrinta intrinsics.
2025-06-30 17:15:26 +01:00
David Green
dcc9e36b18
[ARM] Add neon vector support for floor (#142559)
This marks ffloor as legal providing that armv8 and neon is present (or
fullfp16 for the fp16 instructions). The existing arm_neon_vrintm
intrinsics are auto-upgraded to llvm.floor.

If this is OK I will update the other vrint intrinsics.
2025-06-29 11:37:16 +01:00
Jie Fu
feb61f5b05 [Target] Prevent copying in loop variables (NFC)
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2769:19: error: loop variable '[Reg, N]' creates a copy from type 'std::pair<unsigned int, llvm::SDValue> const' [-Werror,-Wrange-loop-construct]
  for (const auto [Reg, N] : RegsToPass) {
                  ^
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2769:8: note: use reference type 'std::pair<unsigned int, llvm::SDValue> const &' to prevent copying
  for (const auto [Reg, N] : RegsToPass) {
       ^~~~~~~~~~~~~~~~~~~~~
                  &
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2954:19: error: loop variable '[Reg, N]' creates a copy from type 'std::pair<unsigned int, llvm::SDValue> const' [-Werror,-Wrange-loop-construct]
  for (const auto [Reg, N] : RegsToPass)
                  ^
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2954:8: note: use reference type 'std::pair<unsigned int, llvm::SDValue> const &' to prevent copying
  for (const auto [Reg, N] : RegsToPass)
       ^~~~~~~~~~~~~~~~~~~~~
                  &
2 errors generated.
2025-06-28 19:29:00 +08:00
Kazu Hirata
094a7087b8
[Target] Use range-based for loops (NFC) (#146198) 2025-06-27 22:07:58 -07:00
Matt Arsenault
4243e502c1
ARM: Add runtime libcall definitions for aebi memory functions (#144974)
Fix bypassing ordinary RuntimeLibcalls APIs for cases handled
in ARMSelectionDAGInfo
2025-06-27 17:43:46 +09:00
Matt Arsenault
b88e1f6a79
TableGen: Generate enum for runtime libcall implementations (#144973)
Work towards separating the ABI existence of libcalls vs. the
lowering selection. Set libcall selection through enums, rather
than through raw string names.
2025-06-27 17:40:43 +09:00
David Green
888f84f72c
[ARM] Return the correct chain when expanding READ_REGISTER (#145237)
This prevents it CSEing multiple nodes together from "volatile"
registers as they would end up with the same chain. The new chain out
should be the chain from the new READ_REGISTER node.

Fixes #144845
2025-06-25 07:08:46 +01:00
Matt Arsenault
73e4f8a71f
ARM: Use member initializer list (#145459) 2025-06-24 17:47:34 +09:00
Matt Arsenault
48155f93dd
CodeGen: Emit error if getRegisterByName fails (#145194)
This avoids using report_fatal_error and standardizes the error
message in a subset of the error conditions.
2025-06-23 16:33:35 +09:00
Matt Arsenault
91439817e8
ARM: Avoid using isTarget wrappers around Triple predicates (#144705)
These are module level properties, and querying them through
a function-level subtarget context is confusing. Plus we don't
need an aliased name. This doesn't avoid all the uses, just the
ones in the TargetLowering constructor.
2025-06-20 09:34:35 +09:00
Matt Arsenault
5bee2c34bd
RuntimeLibcalls: Pass in FloatABI and EABI type (#144691)
We need the full set of ABI options to accurately compute
the full set of libcalls. This partially resolves missing
information required to compute the set of ARM calls.
2025-06-19 19:02:42 +09:00
Matt Arsenault
874a02f05b
ARM: Move ABI helpers from Subtarget to TargetMachine (#144680)
These are module level concepts, and attaching them to the
function level subtarget is confusing. Similarly these other
helpers that only operate on the triple should also be removed
from the subtarget.
2025-06-19 09:38:22 +09:00
Matt Arsenault
97bfb936af
DAG: Move soft float predicate management into RuntimeLibcalls (#142905)
Work towards making RuntimeLibcalls the centralized location for
all libcall information. This requires changing the encoding from
tracking the ISD::CondCode to using CmpInst::Predicate.
2025-06-17 09:42:53 +09:00
Matt Arsenault
aac603c478
ARM: Avoid repeating hardcoded windows division libcall names (#143834)
This is properly set in the runtime libcall info, so query
the name.
2025-06-12 21:20:45 +09:00
Matt Arsenault
3550662c04
ARM: Avoid using getTargetLowering in TargetLowering (#143833)
This is this.
2025-06-12 21:17:48 +09:00
Matt Arsenault
4079ed3c9e
ARM: Move setting of more runtime libcalls to RuntimeLibcallInfo (#143826)
These are the easy cases that do not really depend on the subtarget,
other than for the deceptive predicates on the subtarget class. Most
of the rest of the cases here also do not, but this is obscured by
going through helper predicates added onto the subtarget which hide
dependence on TargetOptions.
2025-06-12 17:35:55 +09:00
Matt Arsenault
505c550e4c
DAG: Assert fcmp uno runtime calls are boolean values (#142898)
This saves 2 instructions in the ARM soft float case for fcmp ueq.

This code is written in an confusingly overly general way. The point
of getCmpLibcallCC is to express that the compiler-rt implementations
of the FP compares are different aliases around functions which may
return -1 in some cases. This does not apply to the call for unordered,
which returns a normal boolean.

Also stop overriding the default value for the unordered compare for ARM.
This was setting it to the same value as the default, which is now assumed.
2025-06-10 10:46:29 +09:00
Matt Arsenault
a082f665f8
ARM: Start moving runtime libcall configuration out of TargetLowering (#142617)
These Module level triple checks implemented in the Subtarget are kind of
a pain and we should probably get rid of all of them in across all targets,
and stick to a consistent set of names.
2025-06-10 10:00:04 +09:00
Matt Arsenault
4455d9d3e3
RuntimeLibcalls: Use iterable enum for libcall types (#143075) 2025-06-06 20:58:18 +09:00
Matt Arsenault
18e94550e1
ARM: Remove unused CondCode field from libcall table (#142616) 2025-06-03 23:02:01 +02:00