137 Commits

Author SHA1 Message Date
Alex Bradbury
033690fffe [RISCV] Make zfbfmin imply the F extension
Our current approach is that if one extension requires another, we make
LLVM treat it as implied. My initial zfbfmin patch failed to do this for
the F extension (documented as a requirement of zfbfmin). This patch
fixes that.

Differential Revision: https://reviews.llvm.org/D151096
2023-05-23 10:10:11 +01:00
Alex Bradbury
a1455de74d [RISCV][MC] Add support for experimental Zvfbfwma extension
Provides MC layer support for Zvfbfwma: vector BF16 widening mul-add.

As currently specified, Zvfbfwma does not appear to have a dependency on
Zvfbfmin or Zfbfmin.

Differential Revision: https://reviews.llvm.org/D147612
2023-05-19 15:37:26 +01:00
Alex Bradbury
b18a819664 [RISCV][MC] Add support for experimental Zvfbfmin extension
Provides MC layer support for Zfbfmin: vector BF16 conversions.

Zvfbfmin does not appear to have a dependency on Zfbfmin as currently
specified.

Differential Revision: https://reviews.llvm.org/D147611
2023-05-19 15:26:25 +01:00
Alex Bradbury
35ff5eba16 [RISCV][MC] Add support for experimental Zfbfmin extension
Provides MC layer support for Zfbfmin: scalar BF16 conversions.

As documented, this extension includes FLH, FSH, FMV.H.X, and FMH.X.H as
defined in Zfh/Zfhmin, but doesn't require either extension.

No Zfbfinxmin has been defined (though you would expect one in the
future, for symmetry with Zfhinxmin). See issue
https://github.com/riscv/riscv-bfloat16/issues/27.

Differential Revision: https://reviews.llvm.org/D147610
2023-05-19 15:17:56 +01:00
Craig Topper
57a9522f87 [RISCV] Remove redundant F and D extension implication from V. NFC
We recently added implications for F and D to Zve32f and Zve64d
which V implies. So these have become redundant.
2023-05-10 10:00:59 -07:00
Jianjian GUAN
7ab9478560 [RISCV] Make Zvfh depend on Zfhmin.
According to the v spec, the Zvfh extension depends on the Zve32f and Zfhmin extensions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150016
2023-05-10 09:46:19 +08:00
WuXinlong
6b55e9117e [RISCV] Add MC support of RISCV zcmp Extension
This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

co-author: @Scott Egerton, @ZirconLiu, @Lukacma, @Heda Chen, @luxufan, @heyiliang, @liaochunyu

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132819
2023-05-08 14:29:50 +08:00
Craig Topper
728b8a1398 [RISCV] Make zve32f imply F and zve64d imply D.
The 1.0 vector spec PDF has text that says that Zve32f is compatible
with F or Zfinx and that Zve64d is compatible with D and Zdinx.
The references to *inx were removed from the spec in the github repository in
October 2021. The 1.0 pdf was made in September 2021.

Relevant commit 6fedb869e2

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D150021
2023-05-06 23:17:16 -07:00
WuXinlong
9f0d725744 [RISCV] Add MC support of RISCV zcmt Extension
This patch add the instructions of zcmt extension.
[[ https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.0-RC5.7 | spac is here ]]
Which includes two instructions (cm.jt&cm.jalt) and a CSR Reg JVT

co-author: @Scott Egerton

Reviewed By: kito-cheng, craig.topper

Differential Revision: https://reviews.llvm.org/D133863
2023-05-03 22:06:37 +08:00
4vtomat
74c1fa60b5 [RISCV] Add Smaia and Ssaia extensions support
This patch implements 1.0-RC3:
https://github.com/riscv/riscv-aia/releases/download/1.0-RC3/riscv-interrupts-1.0-RC3.pdf

Differential Revision: https://reviews.llvm.org/D148066
2023-05-01 22:30:08 -07:00
Craig Topper
3ce3ee6169 [RISCV] Make Zicntr and Zihpm imply Zicsr.
Zicntr and Zihpm are names for groups of CSRs so they should imply
that CSRs exist.

Reviewed By: asb, kito-cheng

Differential Revision: https://reviews.llvm.org/D148962
2023-04-26 10:11:14 -07:00
Craig Topper
236898f619 [RISCV] Accept zicntr and zihpm command line options
This change adds the definition of the two extensions, but does not either a) make any register definitions conditional on them or b) enabled the extensions by default.

This is somewhat analogous to https://reviews.llvm.org/D143953, but with some key differences.  The best discussion I can find on status is here: https://github.com/riscv/riscv-profiles/issues/43.  These were removed between document version 2.1 and 2.2, but were not defined as new extensions in 2.2.  That addition came later - in March 2022.

According to https://drive.google.com/file/d/1qa57pePesOiDOrNzxuuGFhCL4Rbi9AYB/view these were ratified in March 2023.

Reviewed By: asb, reames

Differential Revision: https://reviews.llvm.org/D144215
2023-04-26 10:11:07 -07:00
Alex Bradbury
52b51ee0d4 [RISCV][NFC] Remove outdated TODOs about extension versions in RISCVISAInfo
As was documented in D147183, we don't currently intend to support
multiple versions of specifications simultaneously. While external
circumstances might mean exceptions to this are needed, the TODOs about
reflecting version numbers in the feature strings no longer make sense.
2023-04-26 09:58:57 +01:00
Eric Gouriou
ca554ad7c2 [RISCV] NFC tweaks in extension descriptions, sorting
NFC changes in RISCISAInfo and RISCFeatures, and matching updates to the
MC tests.

- Drop the '.' in the parentheses section of the Zvk extension
  descriptions. This is supported by
<https://www.masterclass.com/articles/period-inside-or-outside-parentheses#>,
- Remove an extraneous space in the description of Zvt,
- Reorder the ImpliedExts.* constant literals in RISCISAInfo.cpp, as
  suggested in <https://reviews.llvm.org/D148483>.

Differential Revision: https://reviews.llvm.org/D148857
2023-04-21 17:39:44 +01:00
Eric Gouriou
cb7dffdc9a [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)
Update the Zvk support from 0.3.x to 0.5.1, tracking the extension as
documented in
<https://github.com/riscv/riscv-crypto/releases/download/v20230407/riscv-crypto-spec-vector.pdf>.

- Zvkb is split into Zvbb and Zvbc
- Zvbc (vector carryless multiply) requires 64 bit elements (Zve64x)
- Use the extension descriptions from the specification for Zvbb/Zvbc
- Zvkt is introduced (no instructions, but adds an attribute and macro)
- Zvkn and Zvks both imply Zvkt
- Zvkng and Zvksg are introduced, adding Zvkg (GMAC) to Zvkn and Zvks
- In Zvbb, add vrev.v, vclz.v, vctz.v, vcpop.v, vwsll.{vv,vx,vi}

Differential Revision: https://reviews.llvm.org/D148483
2023-04-20 18:25:19 +01:00
Jun Sha (Joshua)
3f81d25cee [RISCV] Remove 'sx' when parsing arch string to match the latest ISA manual
In order to match the latest ISA manual, we need to remove sx prefix.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D148617
2023-04-20 10:32:24 +08:00
Jun Sha (Joshua)
914b38aa4b Revert '[RISCV] Remove 'sx' when parsing arch string to match the latest ISA manual'
This reverts commit fbc63e5658f67036d4ea57940459074d9ecdd2d8
2023-04-20 10:27:02 +08:00
Jun Sha (Joshua)
fbc63e5658 [RISCV] Remove 'sx' when parsing arch string to match the latest ISA manual 2023-04-20 10:19:14 +08:00
Alex Bradbury
c8318b973a [RISCV] Fix canonical ordering of s* vs z* extensions in RISCVISAInfo
As noted in https://reviews.llvm.org/D148315, the ordering logic for
OrderedExtensionMap currently puts s* before z* extensions, but per the
ISA manual the correct order should be z* and then s* (with the
exception of zxm*, which are ordered after s*).

This patch fixes the ordering and adds a TODO for zxm*. The changes are
visible in the test case added in
a35e67fc5be654a7efdfa6125343b90f8960a487 which also demonstrates an
issue with the ordering of single letter extensions (which isn't
addressed in this patch).

This ordering matches the one used by GCC/binutils as well.

Differential Revision: https://reviews.llvm.org/D148615
2023-04-19 07:04:48 +01:00
Alex Bradbury
2a5661c841 [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description
As of
1f03818281
in the riscv-isa-manual, Zfa is at version 0.2. Reviewing the commit
history for
zfa.tex
<https://github.com/riscv/riscv-isa-manual/commits/master/src/zfa.tex>
there are no relevant changes since 0.1. As such, we can simply
increment the version number.

This change also removes the claim in RISCVUsage that we implement a
"subset of" Zfa, as I believe this is no longer true. That sentence
previously incorrectly claimed we didn't implement fli.{h,s,d} (I
[corrected this a couple of weeks
ago](https://reviews.llvm.org/rG3d969191b277)) but I think should have
removed the "subset of" wording too.

As was noted during the review, we never added Zfa to the release notes.
This is corrected in this patch.

Differential Revision: https://reviews.llvm.org/D148634
2023-04-19 06:27:35 +01:00
Alex Bradbury
b582bfb60e [RISCV][NFC] Fix comment in RISCVISAInfo after f98ca363bed
My fault for missing this in initial review -
f98ca363bed7405a23ad4b77167e39505a1ca9dd didn't properly update the
comment to reflect the change.
2023-04-18 09:50:53 +01:00
Jun Sha (Joshua)
f98ca363be [RISCV] Modify arch string parsing order according to latest riscv spec
According to latest risc-v spec, the canonical order in which extension names must appear in the name string specified in Table 29.1 is different from before. In the latest table, non-standard extensions must be listed after all standard extensions. To keep consistent, we now change the parsing order in parseArchString().

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D148315
2023-04-18 16:20:08 +08:00
Nelson Chu
0b9a620b83 [RISCV] Support assembler and dis-assembler for VCIX extension.
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf

Differential Revision: https://reviews.llvm.org/D144530
2023-04-09 20:41:01 -07:00
Craig Topper
dc90af501f [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
New versions I2.1, F2.2, D2.2 A2.1

Make F and Zfinx imply Zicsr.
Make G imply Zifencei.

This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly.

See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D147179
2023-03-30 15:28:44 -07:00
Craig Topper
8c124e3c41 [RISCV] isDigit instead of isdigit for consistency. NFC
There are several other calls to isDigit in RISCVISAInfo.cpp
2023-03-30 00:11:12 -07:00
Craig Topper
24bc5f3f31 [RISCV] Replace std::string with StringRef in RISCVISAInfo. NFC
We're just slicing off part of an existing StringRef. No need to
allocate any new storage.
2023-03-29 22:24:08 -07:00
Craig Topper
e2630a5b4c [RISCV] Use StringRef(&C, 1) instead of std::string(1, C).
We're calling functions that take a StringRef. We can create one
from a single character variable without using std::string.
2023-03-29 21:51:24 -07:00
Alex Bradbury
d3291c692c [RISCV][MC] Add support for the experimental zicond extension
This patch adds the basic MC layer support for Zicond, based on
[1.0-rc1](https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1).
As with other extensions, if there are additional changes between
release candidates without incrementing the version number we won't be
able to reflect that in the version number. I believe we've previously
decided this is not a problem for extensions still considered
experimental (i.e. not yet ratified).

Differential Revision: https://reviews.llvm.org/D146946
2023-03-29 12:17:50 +01:00
Craig Topper
29463612d2 [RISCV] Replace RISCV -> RISC-V in comments. NFC
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449
2023-03-27 09:50:17 -07:00
Alex Bradbury
062065888f [RISCV] Enable tools such as llvm-objdump to process objects with unrecognised base ISA versions
Tools such as llvm-objdump will currently inputs when the base ISA has
an unrecognised version. I addressed a similar issue in LLD in D144353,
introducing parseArchStringNormalized. While it would make sense to
migrate `llvm/lib/Object/ELFObjectFile.cpp` to using
`parseArchStringNormalized` as well, this patch takes a less ambitious
initial step. By tweaking the behaviour of `parseArchString` when
`IgnoreUnknown` is true (which only has one in-tree user), we use the
default supported ISA version when a base ISA with unrecognised version
is encountered.

This means that llvm-objdump and related tools will function better for
objects produced from a recent GCC. This isn't a full fix, as
IgnoreUnknown means that an imafd object with attributes specifying
newer A/F/D versions will have those extensions ignored.

Differential Revision: https://reviews.llvm.org/D146070
2023-03-27 04:32:58 +01:00
Alex Bradbury
af602edf0e [RISCV] Make RISCVISAInfo::toFeatureVector ignore unsupported extensions
parseNormalizedArchString adds a code path that creates a RISCVISAInfo
including extensions that may not be supported by LLVM (rather than
erroring or just ignoring them). Therefore, toFeatureVector needs to
check the extension is supported in order to avoid creating unrecognised
feature strings.

This change shouldn't impact any code paths used outside of test code,
but this will be relied upon by the next patch which moves llvm-objdump
and related tools over to using parseNormalizedArchString.

Differential Revision: https://reviews.llvm.org/D146113
2023-03-26 15:51:38 +01:00
4vtomat
9795aa042a [RISCV] Support vector crypto extension ISA string and assembly
LLVM implements the 0.3 draft specification:
https://github.com/riscv/riscv-crypto/releases/download/v20230206/riscv-crypto-spec-vector.pdf
, and current vector crypto extension version can be found in:
https://github.com/riscv/riscv-crypto.

Differential Revision: https://reviews.llvm.org/D141672
2023-03-25 05:15:55 -07:00
Job Noorman
c39dd7c1db [RISCV][MC] Add support for RV64E
Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570
2023-03-23 12:32:25 +00:00
Job Noorman
d25751779b Bump RV32E version to 2.0
RV32E was recently [ratified](afd613691c) so we should update the version as our MC-layer support is complete.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D144384
2023-03-23 18:12:26 +08:00
Craig Topper
37f3e53c5b [RISCV] Simplify RISCVISAInfo::compareExtension. NFCI
Instead of having a separate single letter and multiletter ranking
use a unified rank that assigns multiletter a larger value than
single letter.

Once we've ranked the extensions, then we compare using these ranks.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D146273
2023-03-20 22:25:11 -07:00
Craig Topper
91b3051ac8 [RISCV] Remove ExtName from RISCVExtensionInfo.
This field is never used in the compiler and was only used in
unit tests added recently.

It's only used as the value in a map where the extension name
is the key. If we need the string we can get it from the key.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146197
2023-03-16 15:20:25 -07:00
Alex Bradbury
cb743dd837 [RISCV] Consistently error for arch strings with trailing _
RISCVISAInfo::parseArchString would sometimes error for arch strings
with a trailing _ and sometimes accept them. This patch makes it
consistently error.

Differential Revision: https://reviews.llvm.org/D145949
2023-03-14 19:12:07 +00:00
Alex Bradbury
b2fad8027a [RISCV][NFC] Small refactor in RISCVISAInfo::parseArchString
Slightly refactor handling of version extraction for the 'baseline' ISA,
to make an upcoming patch easier to review.
2023-03-14 16:37:34 +00:00
Alex Bradbury
e9a03f360f [RISCV] Reject 'g' with explicit version in parseArchString
There is no versioning scheme for the 'g' shorthand for imafd (or in
current ISA specs, imafd_zifencei_zicsr). As such, the only sensible
behaviour to me seems to be to reject a version for it.

Differential Revision: https://reviews.llvm.org/D145954
2023-03-14 12:46:13 +00:00
Alex Bradbury
a159e58c00 Reland [RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString
Prior to this patch, unrecognised z/s/sx/x prefixed extensions were not
ignored when IgnoreUnknown=true.

The first version of this patch, a7313f83b9ca9, incorrectly used
`!isSupportedExtension(Ext)` rather than `!isSupportedExtension(Name)`.
i.e. checked the full substring rather than the split out name, causing
incorrect behaviour when a version is specified. This was fixed and a
new test case addded.

Differential Revision: https://reviews.llvm.org/D145882
2023-03-13 15:19:15 +00:00
Alex Bradbury
7054aa6d6d Revert "[RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString"
This reverts commit a7313f83b9ca904fade446e000550c69e0887cbf.

Causes a buildbot failure.
2023-03-13 11:20:28 +00:00
Alex Bradbury
a7313f83b9 [RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString
Prior to this patch, unrecognised z/s/sx/x prefixed extensions were not
ignored when IgnoreUnknown=true.

Differential Revision: https://reviews.llvm.org/D145882
2023-03-13 10:53:05 +00:00
Craig Topper
de76c016f7 [RISCV] Consistently place single quotes around extension names in error messages.
Some extensions had them, some did not.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D145817
2023-03-10 12:36:37 -08:00
Craig Topper
2800d57e12 [RISCV] Error if F and Zfinx extensions are specified together.
Fixes #61277

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D145809
2023-03-10 11:26:00 -08:00
Craig Topper
90f6a4cc73 [RISCV] Make D extension imply F extension.
I believe this implies relationship is documented in the current
spec but may have been less clear in an older spec.

We used to report an error so I think it should be ok to change this.
Only someone expecting the error should be impacted.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D145125
2023-03-06 19:59:47 -08:00
Alex Bradbury
ff93c9beef [lld][RISCV] Avoid error when encountering unrecognised ISA extensions/versions in RISC-V attributes
This patch follows on from this RFC thread
<https://discourse.llvm.org/t/rfc-resolving-issues-related-to-extension-versioning-in-risc-v/68472/>
and the ensuing discussion in the RISC-V LLVM sync-up call. The
consensus agreed that the behaviour change in LLD introduced in D138550
that results in object files including arch attributes with unrecognised
extensions or versions of extensions is a regression and should be
treated as such. As it stands, this logic means that LLD will error out
if trying to link a RISC-V object file from LLVM HEAD (rv32i2p0/rv64i2p0)
with one from current GCC (rv32i2p1/rv64i2p1 by default).

There's a bigger discussion about exactly when to warn vs error and so
on, and how to control that, and this patch doesn't attempt to address
all those questions. It simply tries to fix the problem with a minimally
invasive change, intended to be cherry-picked for 16.0.x (ideally
16.0.0, but queued for 16.0.1 if we're too late in the release cycle).

As you can see from the test changes, although the changed logic is
mostly more permissive, it will reject some embedded arch strings that
were accepted before. Because the same logic was previously used for
parsing human-written -march as for the arch attribute (intended to be
stored in normalised form), various short-hand formats were previously
accepted. Maintaining support for such ill-formed attributes would
substantially complicate the logic, and given the previous
implementation was so much stricter in every other way, was surely a bug
rather than a design choice.

Surprisingly, the precise rules for how numbers can be embedded into
extension names isn't fully defined (there is a PR to the ISA manual
that is not yet merged
<https://github.com/riscv/riscv-isa-manual/pull/718>).
In the absence of specific criteria for rejecting extensions names that
would be ambiguous in abbreviated form,
`RISCVISAInfo::parseArchStringNormalized` just pulls out the version
information from the end of each extension description.

Differential Revision: https://reviews.llvm.org/D144353
2023-02-25 06:17:50 +00:00
Philipp Tomsich
f68f04d07c [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681
2023-02-24 21:40:42 +01:00
Manolis Tsamis
7b79e8d455 [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144647
2023-02-24 00:35:37 +01:00
Manolis Tsamis
f6262201d8 [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b

Depends on D144002

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144249
2023-02-24 00:17:58 +01:00
Manolis Tsamis
16a6cf6a99 [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144501
2023-02-22 11:15:40 +01:00