1046 Commits

Author SHA1 Message Date
serge-sans-paille
a3c248db87
Move from llvm::makeArrayRef to ArrayRef deduction guides - clang/ part
This is a follow-up to https://reviews.llvm.org/D140896, split into
several parts as it touches a lot of files.

Differential Revision: https://reviews.llvm.org/D141139
2023-01-09 12:15:24 +01:00
Xiaodong Liu
9e06d18c80 [LoongArch] Add intrinsics for CACOP instruction
The CACOP instruction is mainly used for cache initialization
and cache-consistency maintenance.

Depends on D140872

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D140527
2023-01-06 11:41:35 +08:00
Brad Smith
f70d17fc2c [LoongArch] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros

Reviewed By: SixWeining, MaskRay

Differential Revision: https://reviews.llvm.org/D141070
2023-01-05 20:21:22 -05:00
Matt Arsenault
81849497b4 clang/AMDGPU: Remove flat-address-space from feature map
This was only used for checking if is_shared/is_private were legal,
which we're not bothering to do anymore.

This is apparently visible to more than the target attribute (which
seems to silently ignore unrecognized features), so this has the
potential to break something (i.e. see the OpenMP test change)
2023-01-05 16:35:04 -05:00
Zahira Ammarguellat
85d049a089 Implement support for option 'fexcess-precision'.
Differential revision: https://reviews.llvm.org/D136176
2023-01-05 09:35:28 -05:00
Freddy Ye
27b8f54f51 [X86] Support -march=emeraldrapids
Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D140950
2023-01-05 20:27:32 +08:00
Brad Smith
d227c3b68c [Hexagon][VE][WebAssembly] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros

Reviewed By: kparzysz, aheejin, MaskRay

Differential Revision: https://reviews.llvm.org/D140757
2023-01-05 04:45:07 -05:00
David Green
6cac7c285e [AArch64] Alter arm_sve.h to be target-based, not preprocessor based.
This patch makes SVE intrinsics more useable by gating them on the
target, not by ifdef preprocessor macros. See #56480. This alters the
SVEEmitter for arm_sve.h to remove the #ifdef guards and instead use
TARGET_BUILTIN with the correct features so that the existing "'func'
needs target feature sve" error will be generated when sve is not
present.

The ArchGuard containing defines in the SVEEmitter are changed to
TargetGuard containing target features. In the arm_neon.h emitter there
are both existing ArchGuard ifdefs mixed with new TargetGuard target
feature guards, so the name is change in the SVE too for consistency.
The few functions that are present in arm_sve.h (as opposed to builtin
aliases) have __attribute__((target("sve"))) added. Some of the tests
needed to be rejigged a little, as well as updating the error message,
as the error now happens at a later point.

Differential Revision: https://reviews.llvm.org/D131064
2023-01-04 11:22:20 +00:00
Matt Arsenault
f4bcd7f598 AMDGPU/clang: Add builtins for llvm.amdgcn.ballot
Use explicit _w32/_w64 suffixes for the wave size to be consistent
with the existing other wave dependent intrinsics. Also start
diagnosing trying to use both wave32 and wave64.

I would have preferred to avoid the +wavefrontsize64 spam on targets
where that's the only option, but avoiding this seems to be more work
than I expected.
2022-12-29 17:58:55 -05:00
Brad Smith
2784b243e3 [M68k] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros

Fixes #58974

Reviewed By: myhsu, glaubitz, 0x59616e

Differential Revision: https://reviews.llvm.org/D140695
2022-12-29 05:07:35 -05:00
Pavel Iliin
2184fcf17e [AArch64] Fix AArch64TargetParser.def includes for standalone builds. 2022-12-28 17:38:35 +00:00
Pavel Iliin
fe5cf480ee Reland "[AArch64] FMV support and necessary target features dependencies."
This relands commits e43924a75145d2f9e722f74b673145c3e62bfd07,
a43f36142c501e2d3f4797ef938db4e0c5e0eeec,
bf94eac6a3f7c5cd8941956d44c15524fa3751bd with MSan buildbot
https://lab.llvm.org/buildbot/#/builders/5/builds/30139
use-of-uninitialized-value errors fixed.

Differential Revision: https://reviews.llvm.org/D127812
2022-12-27 19:18:07 +00:00
serge-sans-paille
d9ab3e82f3
[clang] Use a StringRef instead of a raw char pointer to store builtin and call information
This avoids recomputing string length that is already known at compile time.

It has a slight impact on preprocessing / compile time, see

https://llvm-compile-time-tracker.com/compare.php?from=3f36d2d579d8b0e8824d9dd99bfa79f456858f88&to=e49640c507ddc6615b5e503144301c8e41f8f434&stat=instructions:u

This a recommit of e953ae5bbc313fd0cc980ce021d487e5b5199ea4 and the subsequent fixes caa713559bd38f337d7d35de35686775e8fb5175 and 06b90e2e9c991e211fecc97948e533320a825470.

The above patchset caused some version of GCC to take eons to compile clang/lib/Basic/Targets/AArch64.cpp, as spotted in aa171833ab0017d9732e82b8682c9848ab25ff9e.
The fix is to make BuiltinInfo tables a compilation unit static variable, instead of a private static variable.

Differential Revision: https://reviews.llvm.org/D139881
2022-12-27 09:55:19 +01:00
Mitch Phillips
744486ec21 Revert "[AArch64] FMV support and necessary target features dependencies."
This reverts commit e43924a75145d2f9e722f74b673145c3e62bfd07.

Reason: Patch broke the MSan buildbots. More information is available on
the original phabricator review: https://reviews.llvm.org/D127812
2022-12-20 17:16:32 -08:00
Steven Wu
9cd6fbee7e Fix module build after TargetParser
Need to include the textual header from the correct module.
2022-12-20 10:31:19 -08:00
Pavel Iliin
e43924a751 [AArch64] FMV support and necessary target features dependencies.
This is Function Multi Versioning (FMV) implementation for AArch64 target in
accordance with Beta Arm C Language Extensions specification
https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning
It supports new "target_version" function attribute and extends existing
"target_clones" one. Also missing dependencies for target features were added.

Differential Revision: https://reviews.llvm.org/D127812
2022-12-20 15:42:25 +00:00
eopXD
1953c7e03b [NFC][RISCV] Extract utility to calculate value through MajorVersion and MinorVersion
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139025
2022-12-20 02:35:10 -08:00
Ganesh Gopalasubramanian
1f057e365f [X86] AMD Zen 4 Initial enablement
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D139073
2022-12-17 16:15:22 +05:30
Fangrui Song
21c4dc7997 std::optional::value => operator*/operator->
value() has undesired exception checking semantics and calls
__throw_bad_optional_access in libc++. Moreover, the API is unavailable without
_LIBCPP_NO_EXCEPTIONS on older Mach-O platforms (see
_LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS).

This fixes clang.
2022-12-17 00:42:05 +00:00
Pierre van Houtryve
678d8946ba [AMDGPU] Add bf16 storage support
- [Clang] Declare AMDGPU target as supporting BF16 for storage-only purposes on amdgcn
  - Add Sema & CodeGen tests cases.
  - Also add cases that D138651 would have covered as this patch replaces it.
- [AMDGPU] Add BF16 storage-only support
  - Support legalization/dealing with bf16 operations in DAGIsel.
  - bf16 as a type remains illegal and is represented as i16 for storage purposes.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D139398
2022-12-13 10:34:26 -05:00
Kazu Hirata
0a4c70feb1 [Targets] Use std::optional in RISCV.cpp (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-09 22:52:29 -08:00
Daniel Kiss
218b77c850 [AArch64][NFC] Move hasFeature fields initiations to the declaration
hasFeature fields need to be initialised to false. Easy to miss as missed for hasPAuth and hasFlagM.
Maybe the code less error prone like this.

Reviewed By: chill

Differential Revision: https://reviews.llvm.org/D139622
2022-12-09 16:23:26 +01:00
Daniel Kiss
7d40baa82b [AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH
Macros are added to ACLE[1] and already added to ARM but these two are missing from AArch64.

[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#changes-between-acle-q3-2021-and-acle-q4-2021

Reviewed By: chill

Differential Revision: https://reviews.llvm.org/D139445
2022-12-07 16:30:16 +01:00
Daniel Kiss
7925e2828e Revert "[AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH"
This reverts commit cfd44221e3e1783c0f44d5b1694dfbe84187246a.
2022-12-07 15:19:31 +01:00
Daniel Kiss
cfd44221e3 [AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH
Macros are added to ACLE[1] and already added to ARM but these two are missing from AArch64.

[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#changes-between-acle-q3-2021-and-acle-q4-2021

Reviewed By: chill

Differential Revision: https://reviews.llvm.org/D139445
2022-12-07 14:52:55 +01:00
Freddy Ye
def720726b [X86][clang] Lift _BitInt() supported max width.
Reviewed By: mgehre-amd

Differential Revision: https://reviews.llvm.org/D139170
2022-12-06 11:02:27 +08:00
Tomas Matheson
541a1371c0 Revert "[AArch64] Improve TargetParser API"
This reverts commit e83f1502f1be7a2a3b9a33f5a73867767e78ba6b.

Did not build with C++20 and caused problems with dynamic libs.
2022-12-05 11:09:03 +00:00
Weining Lu
47edc70866 [LoongArch] Specify registers used for exception handling
See definition in backend D134709 and the doc [1] for more detail.

With the benefit of this change, most libcxx and libcxxabi tests pass.

[1]: https://llvm.org/docs/ExceptionHandling.html

Reviewed By: xen0n, wangleiat

Differential Revision: https://reviews.llvm.org/D139177
2022-12-05 11:42:41 +08:00
Kazu Hirata
35b4fbb559 [clang] Use std::nullopt instead of None in comments (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04 15:57:24 -08:00
Krzysztof Parzyszek
0ca43d4488 DebugInfoMetadata: convert Optional to std::optional 2022-12-04 11:52:02 -06:00
Kazu Hirata
eeee3fee37 [Basic] Use std::nullopt instead of None (NFC)
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated.  The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-03 11:34:27 -08:00
Alex Richardson
f3a17d0595 [clang] Avoid duplicating ProgramAddressSpace in TargetInfo. NFCI
This value was added to clang/Basic in D111566, but is only used during
codegen, where we can use the LLVM IR DataLayout instead. I noticed this
because the downstream CHERI targets would have to also set this value
for AArch64/RISC-V/MIPS. Instead of duplicating more information between
LLVM IR and Clang, this patch moves getTargetAddressSpace(QualType T) to
CodeGenTypes, where we can consult the DataLayout.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D138296
2022-12-01 20:40:58 +00:00
Tomas Matheson
e83f1502f1 [AArch64] Improve TargetParser API
Re-land with constexpr StringRef::substr():

The TargetParser depends heavily on a collection of macros and enums to tie
together information about architectures, CPUs and extensions. Over time this
has led to some pretty awkward API choices. For example, recently a custom
operator-- has been added to the enum, which effectively turns iteration into
a graph traversal and makes the ordering of the macro calls in the header
significant. More generally there is a lot of string <-> enum conversion
going on. I think this shows the extent to which the current data structures
are constraining us, and the need for a rethink.

Key changes:

 - Get rid of Arch enum, which is used to bind fields together. Instead of
   passing around ArchKind, use the named ArchInfo objects directly or via
   references.

 - The list of all known ArchInfo becomes an array of pointers.

 - ArchKind::operator-- is replaced with ArchInfo::implies(), which defines
   which architectures are predecessors to each other. This allows features
   from predecessor architectures to be added in a more intuitive way.

 - Free functions of the form f(ArchKind) are converted to ArchInfo::f(). Some
   functions become unnecessary and are deleted.

 - Version number and profile are added to the ArchInfo. This makes comparison
   of architectures easier and moves a couple of functions out of clang and
   into AArch64TargetParser.

 - clang::AArch64TargetInfo ArchInfo is initialised to Armv8a not INVALID.

 - AArch64::ArchProfile which is distinct from ARM::ArchProfile

 - Give things sensible names and add some comments.

Differential Revision: https://reviews.llvm.org/D138792
2022-12-01 15:30:07 +00:00
Tomas Matheson
d1ef4b0a8d Revert "[AArch64] Improve TargetParser API"
Buildbots unhappy about constexpr function.

This reverts commit 450de8008bb0ccb5dfc9dd69b6f5b434158772bd.
2022-12-01 13:06:54 +00:00
Tomas Matheson
450de8008b [AArch64] Improve TargetParser API
The TargetParser depends heavily on a collection of macros and enums to tie
together information about architectures, CPUs and extensions. Over time this
has led to some pretty awkward API choices. For example, recently a custom
operator-- has been added to the enum, which effectively turns iteration into
a graph traversal and makes the ordering of the macro calls in the header
significant. More generally there is a lot of string <-> enum conversion
going on. I think this shows the extent to which the current data structures
are constraining us, and the need for a rethink.

Key changes:

 - Get rid of Arch enum, which is used to bind fields together. Instead of
   passing around ArchKind, use the named ArchInfo objects directly or via
   references.

 - The list of all known ArchInfo becomes an array of pointers.

 - ArchKind::operator-- is replaced with ArchInfo::implies(), which defines
   which architectures are predecessors to each other. This allows features
   from predecessor architectures to be added in a more intuitive way.

 - Free functions of the form f(ArchKind) are converted to ArchInfo::f(). Some
   functions become unnecessary and are deleted.

 - Version number and profile are added to the ArchInfo. This makes comparison
   of architectures easier and moves a couple of functions out of clang and
   into AArch64TargetParser.

 - clang::AArch64TargetInfo ArchInfo is initialised to Armv8a not INVALID.

 - AArch64::ArchProfile which is distinct from ARM::ArchProfile

 - Give things sensible names and add some comments.

Differential Revision: https://reviews.llvm.org/D138792
2022-12-01 12:50:23 +00:00
Tomas Matheson
f57f086714 [AArch64TargetParser] getArchFeatures -> getArchFeature
Differential Revision: https://reviews.llvm.org/D138753
2022-12-01 12:50:17 +00:00
Alex Richardson
a602f76a24 [clang][TargetInfo] Use LangAS for getPointer{Width,Align}()
Mixing LLVM and Clang address spaces can result in subtle bugs, and there
is no need for this hook to use the LLVM IR level address spaces.
Most of this change is just replacing zero with LangAS::Default,
but it also allows us to remove a few calls to getTargetAddressSpace().

This also removes a stale comment+workaround in
CGDebugInfo::CreatePointerLikeType(): ASTContext::getTypeSize() does
return the expected size for ReferenceType (and handles address spaces).

Differential Revision: https://reviews.llvm.org/D138295
2022-11-30 20:24:01 +00:00
eopXD
d8a27ac0e2 [NFC] Add missing period 2022-11-30 09:07:15 -08:00
eopXD
482b8b493b [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version
According to version_macro.adoc under rvv-intrinsic-doc, the compiler
should have a macro to imply such availability.

Link: https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/version_macro.adoc

Reviewed By: kito-cheng, asb

Differential Revision: https://reviews.llvm.org/D138930
2022-11-30 08:35:53 -08:00
Tomas Matheson
7fea6f2e0e [AArch64] Assembly support for VMSA
Virtual Memory System Architecture (VMSA)

This is part of the 2022 A-Profile Architecture extensions and adds support for
the following:

 - Translation Hardening Extension (FEAT_THE)
 - 128-bit Page Table Descriptors (FEAT_D128)
 - 56-bit Virtual Address (FEAT_LVA3)
 - Support for 128-bit System Registers (FEAT_SYSREG128)
 - System Instructions that can take 128-bit inputs (FEAT_SYSINSTR128)
 - 128-bit Atomic Instructions (FEAT_LSE128)
 - Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
 - Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
 - Memory Attribute Index Enhancement (FEAT_AIE)

New instructions added:
 - FEAT_SYSREG128 adds MRRS and MSRR.
 - FEAT_SYSINSTR128 adds the SYSP instruction and TLBIP aliases.
 - FEAT_LSE128 adds LDCLRP, LDSET, and SWPP instructions.
 - FEAT_THE adds the set of RCW* instructions.

Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/

Contributors:
  Keith Walker
  Lucas Prates
  Sam Elliott
  Son Tuan Vu
  Tomas Matheson

Differential Revision: https://reviews.llvm.org/D138920
2022-11-30 13:37:02 +00:00
Alex Lorenz
60a33ded75 [clang][darwin] Use consistent version define stringifying logic for different Darwin OSes 2022-11-29 14:22:34 -08:00
Archibald Elliott
3e9b6adfc7 [ARM] Move ARM::parseBranchProtection into ARMTargetParserCommon
This should live with the Arm targets, given they have target-specific
target parsers.

Differential Revision: https://reviews.llvm.org/D137835
2022-11-25 11:33:53 +00:00
Fangrui Song
987b49395c [PPC] Undefine __ppc64__ to match GCC
GCC only defines `__ppc64__` for darwin while the darwin support has been
removed from llvm-project. The existence of `__ppc64__` makes some software
think we are compiling for big-endian PowerPC Mac; also it lures users to write
code which is not portable to GCC.

It is straightforward if a distro wants to keep the macro: add
`-D__ppc64__=1` to a Clang configuration file.

Reviewed By: thesamesam, nemanjai

Differential Revision: https://reviews.llvm.org/D137511
2022-11-22 17:01:39 -08:00
Ayke van Laethem
a8efcb96e6
[AVR][Clang] Implement __AVR_HAVE_*__ macros
These macros are defined in avr-gcc and are useful when working with
assembly. For example, startup code needs to copy the contents of .data
from flash to RAM, but should use elpm (instead of lpm) on devices with
more than 64kB flash. Without __AVR_HAVE_ELPM__, there is no way to know
whether the elpm instruction is supported.

This partially fixes https://github.com/llvm/llvm-project/issues/56157.

Differential Revision: https://reviews.llvm.org/D137572
2022-11-23 01:21:09 +01:00
John Brawn
9e3264ab20 [FPEnv] Enable strict fp for AArch64 in clang
The AArch64 target now has the necessary support for strict fp, so
enable it in clang.

Differential Revision: https://reviews.llvm.org/D138143
2022-11-21 16:02:54 +00:00
Krzysztof Parzyszek
7c476697e2 [Hexagon] Add clang flags for v71, v71t, v73 2022-11-18 09:39:47 -08:00
Brad Smith
6536a67338 [Linux] Revert 1e56821bac02a5d3c6249bbf3ef43b8b569d2551
The glibc issue mentioned in #47994 has been fixed upstream.
2022-11-17 19:48:01 -05:00
Ties Stuij
983f63f7f0 [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support
For both ARM and AArch64 add support for specifying -march=armv8.9a/armv9.4a to
clang. Add backend plumbing like target parser and predicate support.

For a summary of Amv8.9/Armv9.4 features, see:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022

For detailed information, consult the Arm Architecture Reference Manual for
A-profile architecture:
https://developer.arm.com/documentation/ddi0487/latest/

People who contributed to this patch:
- Keith Walker
- Ties Stuij

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D138010
2022-11-16 10:20:14 +00:00
Fangrui Song
ea5be2571d [AVR] Fix use-of-uninitialized-value after D137520 2022-11-15 11:06:18 -08:00
Ayke van Laethem
09ab9d4d11
[AVR][Clang] Implement __AVR_ARCH__ macro
This macro is defined in avr-gcc, and is very useful especially in
assembly code to check whether particular instructions are supported. It
is also the basis for other macros like __AVR_HAVE_ELPM__.

Differential Revision: https://reviews.llvm.org/D137521
2022-11-15 15:29:37 +01:00