This is a code optimization patch that does not include feature additions
or deletions.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D140616
This patch fixes:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:1378:16:
warning: control reaches end of non-void function [-Wreturn-type]
std::optional::value() has undesired exception checking semantics and is
unavailable in older Xcode (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS). The
call sites block std::optional migration.
std::optional::value() has undesired exception checking semantics and is
unavailable in some older Xcode. The call sites block std::optional migration.
Add conditional and unconditional branch instructions for loongarch64.
Note that this does not include floating-point branch instructions, that will come in a later patch.
Reviewed By: SixWeining, DavidSpickett
Differential Revision: https://reviews.llvm.org/D139833
This patch fixes:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:1402:18:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
RVD extension is a double-precision floating-point instruction-set extension, which adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard.
This patch:
- Reuse most of the functions in the "F extension" to impl the"D extension"
- corresponding unittests.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D140032
The `EmulateInstructionRISCV` uses a lot of types and functions in `llvm` and `lldb`, this change is to make the code look cleaner.
PS: This patch should be merged before D140032.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D140092
Hardware single stepping is not currently supported by the linux kernel.
In order to support single step debugging, add EmulateInstructionLoongArch
to implement the software Single Stepping. This patch only support the
simplest single step execution of non-jump instructions.
Reviewed By: SixWeining, DavidSpickett
Differential Revision: https://reviews.llvm.org/D139158
Hardware single stepping is not currently supported by the linux kernel.
In order to support single step debugging, add EmulateInstructionLoongArch
to implement the software Single Stepping. This patch only support the
simplest single step execution of non-jump instructions.
Reviewed By: SixWeining, DavidSpickett
Differential Revision: https://reviews.llvm.org/D139158
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated. The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.
This is part of an effort to migrate from llvm::Optional to
std::optional:
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
Some headers in LLDB work only when considered as textual inclusion, but not if one attempts to use them on their own or with a different context.
- python-typemaps.h: uses Python definitions without using "Python.h".
- RISCVCInstructions.h uses RISC-V register enums without including the enums header.
- RISCVInstructions.h includes EmulateInstructionRISCV.h, but is unnecessary since we forward-declare EmulateInstructionRISCV anyway. Including the header is problematic because EmulateInstructionRISCV.h uses DecodeResult which isn't defined until later in RISCVInstructions.h.
This makes LLDB build cleanly with the "parse_headers" feature [1]. I'm not sure what the analagous CMake option is.
[1] I didn't find public documentation but @MaskRay wrote this up: https://maskray.me/blog/2022-09-25-layering-check-with-clang#parse_headers
Reviewed By: labath, MaskRay
Differential Revision: https://reviews.llvm.org/D138310
This patch fixes:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:105:18:
warning: comparison of unsigned expression in ‘>= 0’ is always true
[-Wtype-limits]
Making it easier to understand and harder to misuse.
This only applies to the ReadRegister(const RegisterInfo ®_info) variant.
Depends on D135671
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D135672
All callers were either assuming their pointer was not null before calling
this, or checking beforehand.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D135668
Most of the paths to this never passed nullptr intentionally. Those
that possibly could have were assuming it was not null elsehwere,
so would have crashed.
I've added asserts in those cases.
At least one case was relying on GetAsMemoryData to return an error
when it was given nullptr. So I've hoisted that error setting code
out into the caller.
Depends on D134963
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D134965
WriteRegister and WriteRegisterUnsigned were never pased nullptr,
and only one of them appeared to handle it. Switch to ref to make
the intent clear.
Depends on D134962
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D134963
ReadRegister and ReadRegisterAsUnsigned are always passed valid pointers,
so the parameter should be a ref to make the intent clear.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D134962
The old approach (dedicated ExecXXX for each instruction) is not flexible and results in duplicated code when RVC kicks in.
According to the spec, every compressed instruction can be decoded to a non-compressed one. So we can lower compressed instructions to instructions we already had, which requires a decoupling between the decoder and executor.
This patch:
- use llvm::Optional and its combinators AMAP.
- use template constraints on common instruction.
- make instructions strongly-typed (no uint32_t everywhere bc it is error-prone and burdens the developer when lowering the RVC) with the help of algebraic datatype (std::variant).
Note:
(NFC) because this is more of a refactoring in preparation for RVC.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D135015
All callers have been converted to the optional version.
Depends on D134540
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D134541
We have some 500 ish uses of the bool plus ref version
so changing them all at once isn't a great idea.
This adds an overload that doesn't take a RegisterInfo&
and returns an optional.
Once I'm done switching all the existing callers I'll
remove the original function.
Benefits of optional over bool plus ref:
* The intent of the function is clear from the prototype.
* It's harder to forget to check if the return is valid,
and if you do you'll get an assert.
* You don't hide ununsed variables, which happens because
passing by ref marks a variable used.
* You can't forget to reset the RegisterInfo in between
calls.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D134536
LLVM contains a helpful function for getting the size of a C-style
array: `llvm::array_lengthof`. This is useful prior to C++17, but not as
helpful for C++17 or later: `std::size` already has support for C-style
arrays.
Change call sites to use `std::size` instead.
Differential Revision: https://reviews.llvm.org/D133501
This patch fixes:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h:51:5:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
Add:
- most of instructions from RVI base instructions set.
- some instruction decode tests from objdump.
Further work:
- implement riscv imac extension.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D132789
This patch fixes:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h:34:5:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
and:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:194:21:
error: comparison of integers of different signs: 'int' and 'size_t'
(aka 'unsigned long') [-Werror,-Wsign-compare]
Add:
- `EmulateInstructionRISCV`, which can be used for riscv32 and riscv64.
- Add unittests for EmulateInstructionRISCV.
Note: Compressed instructions set (RVC) was still not supported in this patch.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D131759
